Applied to the phase-locked loop pulse width adjustment circuit design

Preface

In phase-locked loop PLL, DLL and clock and data recovery circuit CDR circuit applications generally require output clock signal has a 50% duty cycle, so that the clock and falling edge is sampling data, maximizing data transfer speed.

In order to meet this demand, we often need to clock output to pulse width adjustment circuitry to get a duty as far as possible to reach 50% of the clock signal.

In recent years was born many kinds of pulse width adjustment circuit.

These circuits can roughly be divided into the following three categories: the first category is the most simple, is produced with 2 divider ratio to 50 percent of the clock, not 2 dividers is designed to adjust duty ratio of, but it did meet this requirements; Secondly, through the use of negative feedback mechanisms, either digital or analog control, adjust the signal duty cycle, this type of circuit is the most important considerations in the system stability; the last one is a complex number arithmetic ratio adjustment circuit, its implementation is relatively complex. Therefore this article focused on the design of the first two types of pulse width adjustment circuit.

2 divider as pulse width adjustment circuit

The vast majority use a fractional PLL 2 prescaler circuit VCO output with high-frequency signal, which implements the feedback path pre-divider requirements, reduces subsequent feedback frequency circuit of working frequency and power consumption, enables output signal pulse width adjustment, the basic met 50% duty cycle.

But its biggest disadvantage that reduces voltage controlled oscillator VCO half of the output signal range, for high-frequency signals in a 50% duty cycle, the more obvious drawback.

Usually we use static D trigger 2-n, in order to achieve when working in high-frequency reducing power consumption, now more and more with dynamic logic circuits 2 crossover.

Figure 1 is a traditional nine pipe implementation of dynamic 2 divider. When the clock DIA for low level, first level clock switch breakover, sampling of the input signal, then the secondary output of the high level of assurance of the circuit of instant output is the previous sample and hold get signal, the signal charge storage in the output node of parasitic capacitance. Because modern CMOS technology has entered the deep sub-micron stage transistor leakage current phenomenon became obvious, therefore, the circuit working frequency should not be too low. When the DIA to high level, the first level of the sampled signal arrives third-level input, DIA's high level allows this level become General inverter, trigger functionality. As a result of the dynamic mechanism, using parasitic capacitance sample and hold signals, reduce the DC circuit, reduce power consumption, and static logic implementation method, the number of transistors. The circuit design, the main clock MOS switch on-resistance, and switch speed compromise and signal rise fall time approximate match. To improve the speed of the circuit, as shown in Figure 2, and the figure 1 circuit switching MOS than clock closer to electricity, therefore faster. On Figure 2 circuit simulation results indicate that the maximum operating frequency circuit can reach 12GHz.

　　

Figure 1 traditional dynamic triggers

　　

Figure 2 improved dynamic triggers

Negative feedback pulse width adjustment circuit

With PLL circuit using negative feedback mechanisms to lock principle similar phase, we also can take advantage of negative feedback mechanisms to construct a simple system to adjust the signal duty cycle.

The system mainly has following several modules: voltage controlled PWM regulator, pulse voltage converter and voltage comparator, etc. System module diagram shown in Figure 3.

Figure 3 negative feedback pulse width adjustment circuit module

Voltage controlled PWM regulator can be used by the voltage-controlled delay line VCDL and phase discriminator PD.

Simple VCDL can consist of a series of inverter, whose output signal is input signal delay, delay size determined by the control voltage VC; phase discriminator PD can be static RS flip-flops. Two of the same frequency there is delay phase detector signal input, the detection of two signal rising edge, i.e. produced pulse width and delay into a linear relationship (★ short delay to a cycle) of the same frequency output, the longer the delay (in a cycle range), PD output signal duty cycle. Therefore, in order to achieve a wide range of signal duty cycle of the regulation, it is important to achieve a wide-range VCDL.

In addition a more simple voltage controlled PWM regulator is PWM expansion circuit, as shown in Figure 4.

The circuit by adjusting signal increase/decrease of delay time to adjust duty ratio of purpose. The diagram near the power of MOS current source of the current size of the control voltage VC. Control voltage is large, NMOS current mirror of current is greater than the PMOS current source of current, the signal rise slower than decline, and vice versa. Therefore, change the size of the control voltage, which implements the signal rise fall delay, thereby achieving a pulse width modulation.

　　

Figure 4 voltage controlled pulse width regulator

Design of the circuit, the transmission signal inverter in MOS with minimum feature size and larger width, the MOS switch rapidly, increasing the operating frequency of the circuit; as current source using MOS, to reduce the Groove length modulation, transistor length should be relatively large, do this to reduce noise.

In addition, it should be noted that, when the control voltage is the power supply voltage half, adjust P, N current source current is basically the same, this requirement to determine their relative width length ratio, to expand the scope of a circuit. Due to the rise in the signal circuit adjustment/decrease of delay time, it is possible in the high-frequency applications will have on the integrity of the signal, so must the circuit output plus buffer, depending on the load capacity of the driver decision buffer. In order to adapt to the requirements of the follow-up module comparison, you need to produce phase complementary signals. The circuit can be composed of twoRP chain. As a result of normal phase path less than RP path, in order to guarantee the level of signal phase complementary, we are increasing the load on that path MOS capacitors, by increasing the normal phase path delay to achieve complementary requirements.

Pulse width adjustment circuit in another module is a pulse voltage converter, its function is to produce and pulse width into the linear relationship between the voltage signal.

This design uses two symmetrical converter for voltage controlled PWM regulator output complementary signal pulse width comparison. If the output clock is 50% duty cycle, its complementary signal pulse width to essentially the same, you two converter's output level is basically the same. Due consideration of the relative value and, therefore, is the voltage pulse voltage conversion process produces a number of non-ideal factors, such as charge and discharge currents do not match, charge sharing, etc., can be ignored. The basic principle of the converter by pulse width control current source for capacitor charging and discharging. In pulse width comparison extreme circumstances, the circuit will also be able to properly reflect the current signal duty cycle of a correct relationship.

System in another module is voltage comparator, the negative feedback system plays an important role.

This design uses the transconductance amplifier OTA on pulse voltage converter output voltage value and produces a voltage-controlled pulse width adjustment for the desired control voltage VC, constitute the entire system of negative feedback loop. The OTA require higher DC gain and greater bandwidth. In order to better guarantee the stability of the entire loop amplifier using level collapsed total source total grid structure. Figure 5 the amplifier circuit.

　　

Figure 5 folding total source total gate transconductance amplifier

When the voltage controlled PWM regulator output signal with about 50% duty cycle, the converter output voltage is maintained at a lower value (considering the charge and discharge-charge roughly the same), so using PMOS tube as amplifiers differential input conforms to the input range of requirements.

In order to expand output range, the amplifier uses a wide range of Cascode current mirror as active load.

After the simulation, the amplifier gain up to 65dB DC, fully satisfy the system requirements.

In order to guarantee the stability of feedback loops, and reduce the ripple control voltage (ripple), amplifier load capacitance should obtain a larger number in order to reduce the frequency of main poles. Consider the area factors, the capacitor can, capacitor NMOS capacitor capacitance per unit area than other types of integrated capacitor should. The capacitor capacitance value is affected by the process, voltage and other factors change is large, and leakage with gate oxide layer thickness decreases and increases, but here you do phase compensation and filtering, you can ignore these shortcomings.

The entire system is important for the stability of the system of loops, the closed-loop system for loop gain is: Loop gain = 1/(1 + s/p1) × A0/(1 + s/p2) as long as the amplifier load capacitance is large enough (about 30pF), you can make the loop has enough phase margin ensure that the entire stability of the closed-loop system.

Typical second order system control voltage stability curve as shown in Figure 6. In PWM voltage converters, we can adopt similar to dianhe pump capacitor charge and discharge structure, or you can use this design uses a simple low-pass filter structure. Considering these two structures introduced in pole position of the p1, the latter has never been easier.

　　

Figure 6 a typical second order system control voltage stability in curves

The system in SMIC 180nm digital technology, the use of Cadence company Spectre emulator through simulation, operating frequency range 100MHz ~ 1.5GHz, stable time around 1 ~ 3 μ s, valid input ratio is 30% ~ 70% output duty errors within the 0.5% basic meets a wide range of application in the required 50% duty cycle design requirements.

The system error mainly from loop limited gain and control voltage ripple jitter on.

In addition, ensure that the voltage pulse width regulator enough range and linearity, are to improve system performance. Therefore in voltage controlled PWM regulator adopts VCDL structure than direct use of pulse width telescopic circuit has advantages, but pulse width telescopic structure implementation is simpler. (Source: today's electronics)