Universal voice based TMS320C50 signal processing system

Summary: Describes a complete PC based and DSP (TMS320C50) of common audio signal processing systems.

The system design can be achieved by programming of different voice signal analysis and processing algorithms, can address different application and new treatment methods, constantly adding DSP module, in order to improve and expand the functionality of the system. In addition, the system also provides high accuracy of voice data acquisition and voice data playback functions, and the entire system for better versatility and high operating efficiency.

Keywords: voice processing digital signal processing chip TMS320C50

　　

Language is important to communicate the information worker.

With the development of modern science and technology, particularly speech communication and voice products widely popular, voice signal digital processing in a growing number of areas play a huge role. Currently, various language signal digital processing of commodities has entered the market, the commercialization of the voice signal processor also has come out, such as KAY company CSL TM (Computerized Speech Lab).

A complete voice signal processing system must not only possess the voice signal acquisition and playback, and more importantly to complete complex speech signal analysis and processing algorithms.

Usually these algorithms operate large, and also to meet real-time or quasi real-time requirements of the fast and efficient processing, the need to adopt high-speed DSP chip. In addition, the requirements for the system to meet better versatility, tailored for different applications and emerging new treatment methods, also making the system easy to improvements and expansion.

To this end, we use the PC as a host to TMS320C50 as signal processing core design of the system, its hardware configuration diagram shown in Figure 1.

Which the United States, Texas Instrument TMS320C50 is the company's 16-bit fixed-point DSP products, it includes improved Harvard (Harvard) structure, high-performance CPU, on-chip memory, on-chip peripheral interfaces as well as a set of efficient discharge of knitting instruction set, computing speed can reach 40Mips, and good price-performance.

1 system structure

System hardware reset as shown in Figure 1.

1.1 PC host

Taking into account the versatility and ease of implementation, we put the CP machine as the system's host, its specific configuration consists of different applications.

It mainly provides system of interactive interface, to control the complete system features.

　　

1.2 PREPROC parts

The whole system adopts a modular structure, flexible configuration, debugging, maintenance, and support software for the digital processing of speech algorithms.

The entire system from a single PC and four modules. These four modules part are the input signal is amplified parts (PREPROC), power amplifier parts (POSPROC), high speed digital signal processing (DSP) and 16-bit high-precision sample playback components (AD/DA). Of these, DSP part complete specific signal processing tasks and control AD/DA part complete voice signal acquisition and playback; PREPROC parts to complete the input audio signal amplification and anti-aliasing filtering; POSPROC part completed smooth filter and amplifier.

The part on the microphone input signal or line I input signals are amplified and anti-aliasing filter processing, its output supply AD/DA parts for sampling.

Its design targets: microphone input range 1mV ~ 31.6mV, line input range 100mV ~ 3.16V, input impedance 10 k Ω, parts adjustable gain, in the nominal range will signal amplification to the AD input for full scale 10V. The anti-aliasing filter as separate plug-ins, detailed design followed by a description.

1.3 POSPROC parts

The part on the D/A rushed out of the analog signal recovery filter and amplifier, its acoustic output supply field.

Maximum power output is used to promote 1W, 8 Ω speakers. Where restoration filter as separate plug-ins, detailed design in the following instructions.

1.4 filter plug-in

This system provides 10kHz and 20kHz two filter plug-ins to choose from.

In order to meet different application requirements, the system can configure different cutoff frequency of the filter plug-in or external filter cut-off frequency is adjustable.

The system provides anti-aliasing filter and recovery filter, respectively two MAX274 and external resistance constitutes of two eight-Chebyshev series low-pass filter.

By device manual phoned MAX274 consists of four similar filter modules, each filter unit is a second order filter filter. For convenience, the four filter unit A, B in turn number, C, D. From the filter precision design "can be found band eight rugged .2DB-Chebyshev low pass filter with normalized parameter B and c, then, can know by MAX274 devices Manual: for each filter unit, are:

　　

In the application, we put MAX274 FC feet grounded, the Rx/Ry = 0.2, it can calculate individual resistance values.

In practice, because resistance is unique, each resistor value shall consist of two precision resistor in series.

1.5 DSP components

The component is a block in the ISA bus half long boards, it controls the AD/DA part complete voice data capture and playback, and download the software to complete the corresponding signal analysis, is the key part of the system.

It consists of TMS320C50 (frequency 40MHz), dual-port RAM (4K8), FIFO (1K8) and the corresponding control circuit.

Use the DSP program host through dual port RAM download to C50 internal procedures.

Sampling, C50, through internal timer Timer to set the AD/DA part of the sampling frequency. Upon completion of a single sample point sampling, AD/DA parts produced C50 hardware interrupt INT1, C50 response interrupt INT1, sampling from AD writes the data to the FIFO, FIFO access the host through reading; voice playback sampling data, in accordance with the playback before the C50 frequency setting internal timer Timer to interruption INT1; playback produced, host to write data to the FIFO, C50 timing response interrupt INT1, read data from a FIFO and compares it to DA output; signal processing tasks are complete, single-C50 internal processing of input and output data through dual port RAM on the host and exchange between the DSP part.

In order to easily write software, here we list the DSP components and PC as well as the AD/DA interface parameters between the parts:

For PC

Dual-port RAM address range is D800H (segment address): 000H ~ 0FFFH (offset address).

The address of the CMD command port is the word design 300H, command as follows:

　　

BIT0: reset the FIFO: BIT1, BIT7: temporarily unused; BIT2: reset TMS320C50; BIT3: PC and C50 handshake signals: BIT4 ~ 6: C50 interrupt INT2 ~ INT4.

State of the address to 0301H STS, status word design is as follows:

　　

BIT0: FIFO2 null flags; BIT1: FIFO1 full symbols; BIT2: FIFO1 half full symbols; BIT3: C50 and PC handshake signals; BIT4 ~ 6 is temporarily not available.

Write address FIFO1 302H, read address 303H.

For DSP

Dual-port RAM address range from F000H to FFFFH.

State the address of STS for PA1, status word is as follows:

　　

BIT5: FIFO1 null flags; BIT6: FIFO2 half full symbols; BIT7: FIFO2 full logo; the remaining bits to be not available.

FIFO2 write address as the address as read PA2, PA3.

The address of the AD as PA8 sampling.

DA adopts two-stage latch, level one latch address is PA11, level 2 latch address is PA10.

1.6 AD/DA parts

The component is a plug in the PC ISA bus half length Board, its maximum sampling frequency, up to 100kHz DSP under the control of the finished part speech data sampling and playback.

The part of the input and output range, resolution 16bit 10V. A/D conversion data to binary complement format, D/A conversion of data format for offset binary code.

　　

　　

2 system software processes

The speech signal processing system in real-time mode or break mode, their software process and structure largely the same.

Here in interrupt mode, for example description of software processes, as in Figure 2 and Figure 3 shows. The entire workflow process, mainly by the host control and DSP interrupt handling process. For speech signal which INT1 sampling and playback; INT2 is used to host the DSP transfer programs operating parameters; INT3 for host to DSP routing DSP program (for different analytical processing have different DSP program). Figure 3 (a) for the DSP master flowchart, Figure 3 (b) for INT1 interrupt service flowchart, Figure 3 (c) to INT2 interrupt handling process, map 3 (d) for INT3 interrupts the flow of services.

3 system debugging results

On various parts of the independent electrical performance testing, all the specification requirements, on the whole system for the FBI.

In the system all electric performance indicator reached the request, and for a lot of software testing, results will meet the design requirements. Currently, the system has been successfully operating at the "speaker recognition" experiment, use it to complete the voice signal analysis, different numbers LPC FFT analysis, real-time spectrum analysis, etc.