FPGA + DSP seeker signal processing FPGA design of key technologies (1)

1 Introduction

As with the anti-industrial requirements for precision-guided weapons, weapons systems, the overall design scheme of increasingly complex, as well as electronic components of rapid development.

Seeker signal processor features more complex, the hardware size increasing PCT processing speed is increasingly high. and product updates quickly, shortening of the life cycle. Implement the functionality, performance indicators, high anti-interference ability is strong, stable and reliable operation, small size, low power consumption, compact structure reasonable, in compliance with the requirements of the missile seeker signal processor is imperative. The last single use DSP processor built signal processor is not able to meet the requirements of .FPGA + DSP seeker signal processing structures become the current and future periods.

FPGA and DSP processors have a very different framework in a device very effective algorithm in another device may be very low.

If your destination requires a large number of parallel processing or the largest multi-channel flow, so simple DSP hardware system may require more space, cost and power consumption. A FPGA on only one device can high up to 550 parallel multiply and add operations to fewer devices and lower power consumption and deliver the same performance. But for regular updates, and decision control coefficient or high-speed serial processing tasks, FPGA DSP optimization level far behind.

FPGA + DSP digital hardware system is a combination of both advantages, both the speed and flexibility.

This article by seeker signal processing system, for example description of FPGA + DSP FPGA technology.

2 system components

This system South a FPGA and DSP to compose a piece, FPGA parallel computation in real-time for standard digital signal processing algorithms capabilities far stronger than the DSP, digital signal processing in the receiving system to use FIR filters, FFT, IFFT, algorithm implemented in the FPGA is much faster than using DSP and FPGA vendor provides a very rich and easy-to-digital signal processing parameters Core. can greatly simplify the development process.

Moreover, the FPGA support chengshi design highly parallel framework and there is a wide range of multipliers and memory resources, digital downconversion (DDC), pulse pressure (PC), moving target detection (MTD), CFAR (CFAR), and so forth, are implemented in the FPGA, which can effectively improve real-time performance, integration and stability. While DSP for other complex signal processing, such as automatic target recognition, anti-jamming, etc.

FPGA and DSP communications through 32-bit data bus interchange.

FPGA by the data bus to be logging target ling information passed to the DSP do post-processing, DSP through data bus control information.

Figure 1 FPGA + DSP system block diagram

3 FPGA design in key technologies

3.1 design across clock domains

3.1.1 basis

Only the most basic logic circuit that uses a single clock.

Most of data transmission-related application has and bovine accompanying challenges that spans multiple clock domain data, such as disk controllers, CDROM/DVD controller, modem, network card, and network processors, etc. When the clock signal from one domain to another clock domain appears in the new clock domain signal is an asynchronous signal.

In the modern IC, ASIC and FPGA design, many software programs can help engineers create millions of door circuit.

But these programs are unable to resolve the signal synchronization issues. Designers need to know the reliable design techniques to reduce the number of circuits in the cross-domain communication time clock failure risks.

Engaged in multiple clock design is the first step to understanding signal stability problems.

When a signal across a clock when the domain for the new clock domain circuit, it is an asynchronous signal. Receive the signal circuits required for synchronization. Synchronization can prevent the first-level storage unit (trigger) of metastable in new clock domains spread spreading.

Metastability is the trigger cannot be a stipulated time period reached a recognizable state.

When a trigger when entering the metastable, especially for the prediction of the unit of transmission}} {level and cannot predict when output to stability in a correct level. The stabilization period, the trigger output some intermediate-level, or may be in a State of oscillation, and this especially with the output level can slip signal channel each trigger cascade communications.

Since the data rate is relatively low, and FPGA working frequency can be very high, so the radar signal processor, FPGA design is bound to introduce cross-clock domain design, for example in a mouth, control network for 10M. Pulse compression work clock 200M, MTD, CFAR as 80M, is a typical design across clock domain.

Figure 2 Schematic clock domains

3.1.2 cross-R '' clock domain processing

[1] [2] [3]