By Xilinx stacking silicon chip interconnect technology depth decryption

1. by Xilinx today announced what products?

By Xilinx uses a called "stacking silicon chip interconnect technology," 3D packaging method, which uses passive intermediary layer, micro-chip bump and Silicon vias (TSV) technology that enables multiple chip programmable platform.

For those who require high density transistors and logic, and calls for a lot of processing power and bandwidth performance for market application, these 28nm platform and chip method, will provide more capacity, more abundant resources and significantly reduce power consumption.

2. by Xilinx so-called "beyond Moore's law" mean?

To date, all process FPGA nodes follow Moore's law, logical capacity doubled the cost reduction by half.

Unfortunately, depend only on the pace of development of Moore's law can no longer meet the markets to achieve controllable power resources as well as higher generation plant yield of endless demand. Stacking silicon chip interconnect technology by Xilinx to launches can effectively address the above challenges of programmable solutions.

3. Why does the customer cannot simply take two or more connected to realization of large-scale FPGA design?

This simple connection method has three main disadvantages: first, the limited number of available I/O is not sufficient to connect to for the partition design different FPGA signal transmission of complex networks, but also difficult to connect to other devices using FPGA system; second, the FPGA signal delay between transmission limits performance; the third is in multiple FPGA I/O devices with standard between create a logical connection will cause unnecessary power consumption.

4. use the stacked silicon chip interconnect technology with no special thermal management requirements?

There is no.

As an intermediary layer as passive, so in addition to the FPGA chip calories, no other thermal problems. Therefore, if such a large monolithic devices can manufacture, uses a tiered Internet technology of Silicon FPGA product is equivalent to a single chip.

5. stacking silicon chip interconnect technology is reliable?

Yes, very reliable.

Due to the relatively thin silicon intermediary layer can effectively reduce internal accumulation of stress, generally stacked silicon chip interconnect technology encapsulates schema of internal stress less than the equivalent size of an individual, this flip chip BGA packaging reduces the encapsulation of maximum plastic strain, thermal and mechanical properties have been improved.

6. stacking silicon chip interconnect technology production of FPGA for those people?

No need to exceed existing logic density levels of high density FPGA customer will be able to benefit from the use of stacked Silicon FPGA technology products on the Internet.

Communications, medical, test and measurement, aerospace and defense, high-performance computing and ASIC prototype design (simulation) market segment customers, when they want to use FPGA to deploy the next generation, the most demanding applications, will have the opportunity to benefit from early supply most abundant resource of FPGA devices. Because there is no in between adjacent FPGA I/O interfaces and PCB alignment to driver IC, therefore previously in the system using multiple FPGA designers, will enjoy the FPGA chip between higher bandwidth, lower power consumption, and faster connections.

7. adopt stacking Silicon products, Internet technology, what are the design guide by Xilinx?

By Xilinx ISE ® design suite that will offer new features, power technology based on stacking Silicon FPGA product design work.

One design rule check (DRCs) and software information to guide the user to implement FPGA chip layout wiring between the logic. In addition, PlanAhead and FPGA Editor enhancements based on stacking silicon chip interconnect technology of FPGA devices illustration effect, helps to develop interactive design layout planning, analysis and debugging. At the same time, we are being prepared and launched you can provide users with the best design practice in detail the guidelines for the application of the manual.

8. the customer must make design partition? software can direct them to design partition?

Software can be automatically allocated to the FPGA chip design, without any user intervention.

If you need to, customers in specific FPGA for logical layout planning. In the absence of any such restrictions by software tools let algorithm intelligently placed within the FPGA logic, and follow the on-chip and chip connection and timing rules.

9. which products will use the stacked silicon chip interconnect technology?

Virtex ®-7 2000T device is the most large-scale Virtex-7 series products, up to 200 000 logical unit, and adopts 36 10.3 Gbps transceiver, it will be the first to adopt this technology products.

The first batch of product is expected to be launched in the second half of 2011.

10. by Xilinx's 7 series product?

2010 June announced the launch of new 28nm Artix ™-7, Kintex ™-7 and Virtex-7 series will power, performance/capacity and price/performance breakthrough innovation in such areas as technology and unprecedented high scalability and productivity perfect together, significantly increased by Xilinx targets design platform for strategic advantage, allowing a broader user base, Terminal market and application can be more easily programmable logic.

All of the 7 series FPGA products are based on the technology implementation of 28nm unified structure, designed for low-power high-performance integration carried out careful optimization. This unique fusion of not only the sharp drop in total power consumption by 50%, the price/performance and system performance both upgrading to 2 x, but also the world's first integrated 200 000 logical unit of FPGA (compared with the previous-generation products, capacity improves 2.5 times). Therefore, designers can now easily meet the demand for applications extended 28nm product family supports a variety of system performance, capacity and cost requirements, and at the same time does not exceed the power budget.

11. when by Xilinx FPGA 7 series launched software?

Support new FPGA series of early ISE ® Design Suite software, has spearheaded the object-oriented early customers and partners.

12.28nm devices when available?

The first batch of products will be 2011 starts in the first quarter.