Based on the shared technology charge pump circuit

Abstract: in order to reduce chip area, increase the charge pump gain, an approach based on sharing of charge pump circuit.

By changing two child charge pump series and connected, you can produce a higher voltage and current driving capability of smaller negative pressure, or you can generate a voltage is low but current drive capacity of large negative pressure, this will not only satisfy the system is in programming and erasure on high voltage requirement, but also saves about 50 per cent of the chip area. Charge pump circuit also took on the p-MOS voltage of substrates for dynamic control. Simulation results show that the charge pump gain increased by approximately 14%. The circuit is particularly suitable where two or more negative pressure to complete the programming and erasing of Flash memory.

Keywords: charge pump; share; the lodge to Flash; drive capability

E-erasable programmable memory (memory, EEPROM electrically-erasableprogrammable read-only) and Flash memory in programming and erasing operations require high pressure, therefore charge pump circuit in the single power of embedded memory chip play an extremely important role, their power consumption, size and low power supply voltage of working capacity, directly affects the performance of the entire storage chip.

But in practice, a memory chip inside usually require more than a positive pressure and negative pressure, so the system will require multiple positive high-voltage charge pump and negative voltage charge pump, which makes the charge pump the chip area over the entire memory chip in half of the external circuit. For a band-tunneling thermal electron injection (band-to-bandtunneling induced hot electron, BBHE) programming p channel DINOR (p-channeldivided bit-line NOR) structure of Flash memory, it requires at least one positive high-voltage charge pump and two negative voltage charge pump. For source-induced band-tunneling thermal electron injection (source induced band-to-band hotelectron_, SIBE) way to program new Flash memory, the system will need 2 is high voltage charge pump and 3 negative voltage charge pump.

Because the charge pump circuit in occupies an area of very large, especially when the power supply voltage gradually reduced from 5V to 1 .8V even 1.2V, to produce sufficient pressure to charge pump must increase progression or increase the size of the coupling capacitance, which makes the charge pump circuit in occupies an area of increasing.

Therefore charge pump sharing technology to reduce chip area is very important, but this either increases the difficulty of the process, or making circuit structure become very complex.

This article by changing the charge pump series and connected relationships, without adding any process difficult and circuit complexity, has realized the charge pump shared, making the charge pump circuit in occupies an area of greatly reduced.

1 sharing technology charge pump structure and working principle

Table 1 gives the SIBE structure Flash memory of typical operations mode, including programming and place line-high pressure required 3.3 V is greater than 100 μ A driver's ability to achieve a number of data while programming.

Figure l is used for charge pump system diagram, 8V and 5V charge pump used to produce a 8V programming Word line voltage and 5V erase source line voltage Vpp,-8V and-3.3V charge pump is a shared technology charge pump circuit, it can produce-8V (drive capability greater than 10 μ A) line erase voltage and-3.3 V (drive capability greater than l 00 μ A) bit line programming voltage Vnp.

Whereas-4.8V charge pump you have to select grid 4.8V high pressure on-Vnc to put-glow programming voltage is passed to the select storage unit, as well as in-line voltage conversion module. Clamp circuit is used to output voltage to clamp so that output-voltage stability in the required voltage values. In circuit stopped working, through the discharge pathway can output voltage reset to OV.

　　

　　

In order to reduce chip area, based on the share of negative voltage charge pump circuit shown in Figure 2, it can produce-8V and-3.3V two negative pressure, Ve and Vp is a high-voltage control signal, Ve can Vnp and convert between supply voltage VDD, Vp can-convert between 4.8V and VDD, one-source-4.8V 4.8V charge pump.

The relationship between the input and output as shown in table 2. When you need to produce-3 .3V, let Ve equal to VDD and reset the Vp-4.8 V, the system can be regarded as two of the three levels of child charge pump

(M1-M4 respectively by PMOS tube, coupling capacitor C1-C3 and PMOS tube M5-M8, coupling capacitor C4-C6 composition) in parallel, in two non-overlapping clock CKl and driven by CK2, Vnp output-3 .3V, connect to C3 and C6 of clock signals respectively CKl and CK2, so two child charge pump in one clock cycle, respectively, on the output of the Vnp re-charging.

This not only significantly reduce output voltage fluctuations, while also increasing the output drive capability to meet a number of simultaneous programming on demand of the driving current. If the system needs-8V, Vp of high voltage to VDD and connect to the Ve high pressure output Vnp, M10 is off, but in the beginning because Vnp-0V, M9 does breakover, electric circuit remains two child charge pump parallel work status, but their output is M10. With the Vnp becomes smaller by 0V, its voltage to voltage below the node N2, M9 will gradually breakover, the system can be thought of as a six-level of the charge pump (by M1-M4 and M6-M8 and C1-C6 composition), the final system will produce a high-8V. In this way, and the use of two separate charge pump produces-8V and-glow method compared to the charge pump can save about 50 percent of the chip area. Note that M6-M8 substrate voltage control by Vsub, mainly in order to reduce their side effects, the increase in the lining of a charge pump of gain.

　　

　　

Sharing technology charge pump Ve, Vp timing shown by Figure 3 voltage conversion module.

Figure 3a can achieve Ve in the VDD and conversion between vnp and Figure 3b for Vp at VDD and-4.8V between the conversion. Combined with Figure 2, its working mode are shown in table 2. When a control signal is high, Vpe charge pump produces-8V voltage, and when Vpe to low, charge pump high pressure generated-3.3V.

In order to reduce the share charge pump PMOS in liner partial effects tube, increase the charge pump gain, this article uses a substrate voltage control module, see Figure 4 below.

Which connect the Vnp-8V and-3.3V charge pump output, Vpe is a control signal. Which NMOS tube Mw1 and MN2 and PMOS tube Mp2 and MP3 form on the current mirror. When Vpe-OV, the module will not work, the node is equal to the OV V3, the output voltage is equal to VDD Vsub, and sent to Vsub in Figure 2, and charge pump produces-3.3V high pressure. When Vpe is high, the module starts work, with charge pump in Figure 2, 0V Vnp will gradually reduce the conduction of MH PMOs tube capacity increases, Mp3 and the gate voltage Mp2 will gradually decrease, so that the capacity of the Mp2 is gradually increasing, via inverter input voltage will rise gradually from OV, ultimately inverter INV start flipping, Vsub voltage VDD from initial into OV. By adjusting the chart PMOS and NMOS pipe dimensions ensures that when the Vsub become OV, Figure 2 PMOS tube Mp6-Mp8 of p-n junction is not being bias. This reduces the effect of substrate bias Mp6-Mp8, improves the charge pump of gain.

　　

　　

2 simulation results

To verify this charge pump performance with Tsinghua University microelectronics developed by 1.4 μ m high pressure process parameters, use software HSPICE simulation on it.

Where the high voltage NMOS tube 0.7 V threshold voltage, high-voltage threshold voltage PMOS tube-0.8V. Optimized coupling capacitor C1 to C6 are 12pf, the clock frequency, the power supply voltage VDD 20MHz as 5.0V.

Figure 5 is a charge pump circuit analog waveforms.

Where is the control signal, Vwkrk when Vwork as high, input clock CKl and CK2, charge-pump circuit begins work. When Vwork to low, the clock stopped, charge-pump circuit does not work, just venting channels of the output-side Vnp to charge relief. We can see from Figure 5, when Vpe to low, Vp-4.8V, Ve equal to 5.OV, charge-pump circuit output voltage Vnp equals-3.3V. When Vpe is high, Vp is equal to the Ve and 5.0V Vnp voltage, final system output voltage Vnp equals-8V. And you can see, when the negative voltage charge pump work for a period of time after the Vnp reach-5V, Vsub voltage 0V by 5.0V becomes, which reduces the lining of PMOS tube Mp6-Mp8 allows partial effect of high pressure output Vnp waveform on a turning point for Ncg, and voltage drop after corner speed significantly increased and ultimately achieve-8V (dotted portion is not used substrate voltage control module Vnp waveform, its voltage drops to-eventually 7V), this makes the charge pump gain increased approximately 14 per cent.

　　

　　

3 conclusion

This article proposes an approach based on sharing of charge pump circuit, by changing two child charge pump series and connected, you can in the same circuit in the two negative pressure, saving approximately 50 per cent of the chip area.

Through a substrate voltage control module to charge pump PMOS voltage of substrates for dynamic control, make the charge pump gain increased approximately 14 per cent. The circuit is particularly suitable where two or more negative pressure to complete the programming and erasing of Flash memory.