Infrared image processing platform real-time histogram Equalization of SoC implementation (1)

　

O introduction

Histogram equalization is infrared image processing simple and effective method of image enhancement [1].

Histogram equalization in enhanced goals while zoomed in backgrounds and noise signal, therefore was raised platform histogram equalization algorithm, which can achieve enhanced objectives and better noise suppression of background and purpose [2,5], has great practical value.

Traditional histogram Equalization and platform histogram equalization with compute and storage capacity weaknesses, real-time image processing applications.

The lookup table structure approach can significantly reduce the amount of storage and computation, can realize real-time processing. Affected by the level of development of electronic technology, from published papers, past most real-time histogram equalization with hardware structure is too complex and expensive, inflexible software defects in application has great limitation [2, 4].

Use a subject in France Sofradir company 288 x4 of linear array infrared detector, the detector output per column 288 image data, 12-bit image data transfer rate of 16 MHz/s per second for about 5 million more output column data in real-time to grayscale transform is the subject of the basic requirements.

After extensive research, subtly introduces Altera Corporation FPGA (field programmable gate array) technology latest achievements N I o s Ⅱ soft core microprocessor, was substantially simplify the hardware design, and finally, the platform real-time histogram equalization algorithm able to SOC (System on chip).

1 platform histogram equalization algorithm theory

Histogram of the image is the image in each of the gray-scale with a frequency of the statistical relationship between.

It can give a general picture of the image, such as the image's description of gray areas, each level grayscale frequency, etc., is a single-dimensional discrete functions:

Type: L-site image in grayscale; p (k) to KTH shades of probability density; nk to KTH shades that are contained in the number of pixels; n is the site the number of pixels in the image.

Platform histogram equalization is when the histogram equalization on grayscale weights set upper and lower limits of the two platforms, when a level grayscale pixel count is greater than or less than the upper or lower platform, the weight is active in the maximum or minimum value so you can avoid the transformed, such as large cloud too large-area occupies the background of dynamic range, which is interested in the details section to allow headroom.

Topic of request 4 096 to 256 pixel level compression level, and the original image data is not possible to occupy the O-4 095 of each level, if the original image data in pixel-level maximum Nmax, minimum of Nmin, through simulation to pixel-level from the Nmin ~ Nmax mapped to O a 255.

Set map after I-level grayscale pixel number ni, CDF (I) is a cumulative distribution function, P1 and P2 are the set of upper and lower limits of the platform value, the algorithm is as follows:

　　

　　

2 platform histogram Equalization of SOC implementation

From infrared detector front-end signal conditioning circuit output signals with 12-bit data signal data, the pixel clock signal clk_16M, columns, sync signal clk_l (low level), frame sync signal clk-f (low level).

Figure 1 is a time-series chart, clk clk a 64M 32M and is a 16M by PLL clk 2 multiplier and 4 times the rate of output clock.

As needed, pixel in each number on the grayscale tab just a 4 k memory 24 bit× can meet the application requirements; gamma lookup tables only need 8 bit× 4 k memory to meet application requirements.

In the real-time applications, the number of pixel grayscale tab and grayscale lookup tables in table tennis, so the system total storage of 32 bit× 8 k. There are many less expensive FPGA in incorporates meet the application requirements of programmable memory resources, so memory can be integrated in .FPGA. If the algorithm logic control and arithmetic operations are integrated in FP-GA, algorithm can achieve SOC.

Algorithm involves a large amount of a division operation, Division calculator will consume a large number of logic resources FPGA and wiring (Altera FPGA company: for example, a 16-bit parallel divider consume about l 000 LE (logical unit) and chip most wiring resources), in order to increase the speed of the performance and stability of the circuit run plus the number of level lines, logical resource and resource consumption is the wiring has increased by leaps and bounds.

Excessive logical resources especially wiring resource consumption will make circuit speed performance significantly reduced, sometimes can't even design, so that the adapter failed. Obviously, this kind of design is not reasonable. Ahera company latest N I o s Ⅱ soft core microprocessor provides a good solution. The processor is able to very small hardware cost in exchange for a high performance (600 ~ 700 LE of logic resources and a small amount of wiring resource consumption), the current capacity of the FPGA are relatively large, design simply consumed not so many resources, chip remaining hardware resources, more often than not I o N s Ⅱ soft core processor consumes more hardware resources, design often will not increase the cost of the hardware. It is different from a traditional microprocessor, has the following characteristics:

A) offers a wide range of free IP core, such as the microprocessor core N I o s Ⅱ, timer/counter, serial ports, DMA, SDRAM, SRAM, SBRAM, .Flash controller, users can choose to build their own IP cores for embedded systems, system offers flexibility.

B) provides user-friendly hardware and software design and development environment, the hardware design process and the same traditional FPGA design, software design support

Standard c programming language, development environment offers a wide range of library functions for user support JTAG debug called, and software debugging and debug an existing popular microprocessors in the same way as, in addition, combined with the hardware environment, you can accomplish many design simulation, most of this functionality is not available in traditional microprocessor. C) support for embedded operating system of the transplantations.

D) support for 32-class outages.

Use N I o s Ⅱ soft core microprocessor, to avoid the spread of high-performance microprocessor hardware design of complex, platform real-time histogram equalization scheme as shown in Figure 2.

　　

　　

Figure 2, table 1, table 2, lookup tables 1 and 2 are lookup table dual-port RAM, working in table tennis.

16 MHz pixel clock with FPGA PLL multiplier to 32 MHz and 64 MHz, the pixel clock falling edge of latch column synchronization, synchronization and data signals, and the latch signal and multiplier clock to sequential controller will latch frame synchronization signal in its drop along the second frequency generated high and low level signal used to distinguish between odd and even frame.

Figure 2 works as follows: when working in the odd frames, table 1 dual-port RAM realtime complete pixel grayscale number of statistics, statistical table 2 does not work; the lookup table l complete real-time gamma find jobs, find the table 2 does not work.

Statistical tables of works as follows: when a latch column synchronous signal to a low level, will latch data signal as a dual-port RAM read port and write port addresses signal, use the reverse signal clk_16M as dual-port RAM read enable signal, use clk_64M as dual-port RAM drive clock signal; when clk_16M for high level and clk a 32M for low level, in the clk a 64M rising will read out the number of pixel grayscale plus 1, when a high level and clk_16M clk 32M as high a level, use the write-enable clk_32M as signal, in clk-64M rising number will be written to grayscale, grayscale tab 1 dual-port RAM. After the above actions, you can complete a pixel number of statistical work. At this point, the latch data signal as a lookup table l dual-port RAM read port address signals elk_16M as dual-port RAM read-driven clock, columns with latch signal of anti trust, and the reverse signal delay a pixel clock cycle of signals and signal as a dual-port RAM read enable signal (because dual-port RAM belt level line, so you cannot simply be column synchronized back to believe, as the reading of the signal), real time output transforms grayscale data, column synchronization and synchronization output similarly to consider the line of dual-port RAM. When the frame synchronization signal is high level, sequential controller to N I o s interrupt signal 1 issued Ⅱ, N I o s Ⅱ interrupt signal is received, the Read tab 1 1 pixel grayscale in counting values, complete gamma lookup tables for the calculation and processing of grayscale lookup table is written to the lookup table 1, table 1 in the data-0. When working in a couple of frames, the module's work and the odd frame instead. N Nios serial port used to receive the set of platforms and platform value. Serial work in break mode, the interrupt has the highest priority. Serial port to the starting character + platform command + platform value 24 bit data + ending character + checksum "communication protocols for data reception, reception, the serial port to send port to receive the start character + correctness command + ending character + checksum" Transfer Protocol up bit machine FA Huigao signal.

3 design and experimental results

Design found two issues must attach great attention:

A) tables read-write port signal affected by infrared detector front-end circuit output signal and N I o s Ⅱ signal switching control, if the control properly, it is easy to produce a logical confusion.

Recommends that each time you switch can control before the signal to an invalid state, and then set the clock signal to a high level, switching the control signal, and then switch the clock drive signal and data signals. But every time I o N s Ⅱ in reading values in the statistics, it is best to have a small delay program, first data read 2 times. Because the system each time the switch's one I o N s, s Ⅱ complete a grayscale solution and removal of 0 does not require such a long time, every time you complete the solution and 0, read and write to the port control signal from the detector front-end circuit output signal control. After this process, the system is stable and will not appear logical confusion.

B) serial port interrupt has the highest priority, but also with [1] [2]