G.726 Audio codec in the realization of the SoPC

ITU G.726 is formerly CCITT in 1990 in G.721 and G.723, on the basis of criteria relating to non-linear PCM signal 64kbps converted to 40kbps, 32kbps, 24kbps, ADPCM signals of 16kbps.

G.726 standard algorithm is simple, the voice quality is high, many converted voice quality guaranteed, to be able to achieve low bit rate voice quality network level, allowing voice and voice transmission has been widely applied.

G.726 voice compression algorithm has been able to DSP core devices DSP application system implementation.

But developing DSP processor core DSP application system development method used is the bottom-up design processes, seriously affect the efficiency of development and success. In the face of modern communications technology, DSP processor hardware structure of the exposed immutability, processing speed is slow, and so on. Modern high-capacity, high speed development of FPGA and its related technologies, reconfigurable DSP applications, DSP data throughput and data of pure hardware processing, has unique advantages. New FPGA DSP system-level development tool and a complete software development platform that allows designers to use top-down development method for FPGA DSP design, design to be very efficient.

　　

This article describes the G.726 standard that gives the design of DSP FPGA-based development process, using MATLAB/Simulink, ALTERA Corporation of DSP Builder and SOPC Builder tool designed voice recording SoPC system G.726 Audio codec, and implements the codec in the system.

Using FPGA-based G.726 Audio codec for voice recording embedded system has run fast, small, short development cycle and other advantages.

1 G.726 Audio codec standard

G.726 encoder block diagram shown in Figure 1.

G.726 Audio codec first entered A law or μ law log-PCM signal S (k) converted into linear PCM code Sl (k), and then and prediction of signal Se (k) subtraction produce differential signal d (k), then the difference signal adaptive quantization, produces 2 ~ 5 bit ADPCM coding I (k). On the one hand I (k) will be sent to the decoder; on the other hand inverse Adaptive quantizer use I (k) produces quantifiable difference signal dq (k). Prediction of signal Se (k) and quantified differential signal dq (k) are added to produce local reconstruction Sr (k). Adaptive Predictor is a second-order poles and 6-order a la carte composition of filter, under reconstruction Sr (k) and quantified differential signal dq (k) input signal prediction signals Se (k). Quantizer scale factor Adaptive unit based on the input signal of calculating quantizer scale factor y (k), used to control the quantity and inverse quantizer for adaptive capabilities. Quantizer scale factor from fast and slow factor in two parts, as well as speed control factor al (k) on the part of weighted. Al speed scaling factor (k) computes the adaptive speed control unit and tones and transfer test detection unit is complete.

G.726 Audio codec decoding process actually already included in the programming, just much output PCM format conversion unit and synchronous serial code adjustment unit.

Output PCM format conversion is the linear PCM code is converted to A law or μ-law PCM code; synchronous serial code adjustment is to prevent multiple transmission, conversion errors.

2 FPGA-based DSP design and development process

Use of traditional development tools, based on FPGA DSP developers after the algorithm determines that can only be working directly with VHDL or VerilogHDL voice for FPGA DSP system design, development requires a longer period, and the degree of difficulty is relatively large.

Current FPGA DSP development tools, such as DSP Builder, SOPC Builder, Generator, etc., allowing SYSTEM designers to follow a similar to software development and design process for FPGA DSP design, design to be very efficient.

This use of MATLAB/Simulink and Altear company development tool for FPGA-based DSP design development process.

DSP Builder of ALTERA Corporation launches DSP-oriented development of system-level tools. It serves as a Toolbox for MATLAB Simulink (ToolBox). MathWorks MATLAB and Simulink system-level design tools have the algorithm development, simulation, validation, DSP Builder will these instruments and ALTERA development tools together, providing users with a complete DSP development platform.

The design of DSP FPGA-based system-level development flow as shown in Figure 2.

Its steps: (1) in MATLAB/Simulink for DSP system modeling, graphical way called ALTERA DSP Builder and other Simulink library image module (Block), constitute the system level and algorithm design diagrams, using Simulink complete model simulation. (2) the use of DSP Buider Simulink model files will (.mdl) into common hardware description language VHDL file (.vhd), conversion to HDL file is based on RTL VHDL description. (3) on the conversion process in VHDL RTL code for synthesis and simulation file, compile the adaptation and simulation. TheTools can be an ALTERA Quartus II software, and can also be a third-party software tools. (4) in the DSP Builder directly downloaded to the FPGA Development Board, the user can also be completed through the Quartus II, test the hardware of the download. The entire development process is almost in the same environment is complete, the actual realization of the top-down design processes, greatly reducing the DSP design cycle.

3 G.726 Audio codec in the realization of the SoPC

3.1 G.726 standard algorithms simplify

This design of codec is in voice recording system G.726 proposed rate Kbps ADPCM algorithm, according to the actual situation on the algorithm, some simplified and improved.

Specific simplified as follows: (1) because this system codecs of the input signal is linear PCM coded, PCM code conversion module can be omitted.

(2) of this algorithm is used in a pure voice storage, you can not make tone/transition tone detection. (3) on the quantizer scale factor y (k) updated to simplify. Y (k) for update evaluates to:

y(k)=a1(k)yu(k-1)+[1-al(k)]yl(k-1) (1)

Normally, only the voice signal, al (k) is tending to 1; when the input signal for a smooth, al (k) of the value is between 0 and 1.

On voice storage system, enter only the voice of roughly think al (k) the approximation of the value is 1, which will be calculated quickly scale factor yu (k) directly as new y scale factor (k), y (k) = yu (k-1), reduce the complexity of the algorithm.

　　

3.2 G.726 algorithm in modeling in Simulink

In Simulink using ALTERA DSP Builder library module build for FPGA fixed-point implementation models.

Here the model design G.726 encoder. The entire design uses a multi-level structure, top-level design model includes multiple subsystem model model, such as adaptive quantizer subsystem model, inverse Adaptive quantizer subsystem model, the quantizer scale factor Adaptive subsystem model. The following key analysis encoder system top design model and adaptive quantization for subsystem model.

3.2.1 Encoder top design model

Top model provides external PCM voice interface, it also provides for Avalon bus interface which enables the design of the encoder model integrations by SOPC Builder for Nios II system of a peripheral device.

Model of adaptive quantization and inverse Adaptive quantizer model, most of the scale factor Adaptive module and adaptive forecasting module SubSYSTEM for HDL. Encoder top design model as shown in Figure 3.

Which DSP Builder SignalCompiler module is the heart.

Its main features include: (1) into the Simulink design can be integrated RTL VHDL code; (2) generate VHDL testbenches; (3) for LeonardoSpectrum, Synplify and Modelsim third party EDA tools generate Tcl script file; (4) the simulation for Quartus II produce simulation vector file (.vec); (5) PTF profile, is used to design automatically lose to SOPC Builder tool. SignalCompiler control design system, compile, and simulation of processes.

According to the needs of the G.726 Audio algorithms, the system requires two clock, respectively, 8kHz and 120kHz 120kHz for Adaptive Predictor subsystem.

Therefore need to model using PLL module PLL clock design implementation to produce the required two clock, DSP Builder under PLL output rising edge of the clock. In Simulink design will not be displayed on a time series model clock pins, but when the system into SignalCompiler VHDL file automatically put the time series module clock pins are connected with the clock.

3.2.2 encoder Adaptive quantizer subsystem model

Adaptive quantization for the model as shown in Figure 4.

Adaptive quantization in logarithmic domain, in comparison with quantified differential signal on normalized after processing, through to find the quantizer specification of input/output characteristics, i.e. be ADPCM yards. Logarithmic operations in realization of Simulink is with lookup tables, use the DSP Builder child library LUT module; specifications of input/output characteristics table implementation is to use ROM look-up, EAB with ROM module implementation.

Because ADPCM audio codec algorithm eventually be implemented in the FPGA, Simulink in floating point values must be converted to a fixed value in the destination hardware implementation.

Hardware fixed-point value expressed in digits and a decimal point position not only affect the composition of hardware system resource utilization, also affect the system's characteristics. The design of the application according to the signal to determine the location of the decimal point, and according to the actual need to change the number of digits to the right of the decimal point in order to save hardware resources, flexibility in the application bus control library module to the total number of stop bits, bits, bit extraction or data type conversion, and so on, to meet the requirements of accuracy.

　　

3.3 G.726 count

Model of simulation process

Using MATLAB/Simulink and DSP Builder tool for FPGA-based DSP design requires a series of simulation.

In the design of models in Simulink first in Simulink simulation, not only verify the accuracy of the model, but because for ModelSim simulation TestBench file in the incentive is the input signal from the simulation based on Simulink SignalCompiler structures, and can only be used after the simulation SignalCompiler VEC file conversions. In Simulink simulation validation in completed, using the model design SignalCompiler.

For the design of the converted file, generated by VHDL RTL simulation must be carried out.

Because the Simulink model simulation is in the algorithm class, while generating VHDL description is RTL, both describe situation can not be fully compatible with, so you need to generate RTL VHDL code for functional simulation. Simulation can be run by Modelsim conversion process generated by the Tcl script file. Finally you can use conversion process generated VEC file, in the Quartus II software sequential simulation.

This design on the modeling of speech coder completes the simulation, Simulink simulation results indicate that the design of speech coder has achieved the expected results.

3.4 codec model in the comprehensive system SoPC

Quartus II encoder model in integrated and compiled, you can use the SOPC Builder will add it as a peripheral to a Niso II system.

SignalCompiler generated PTF configuration file can be used to design automated output to SOPC Builder tool. The design of the encoder SOPC Builder appears in the module pool, add it to the created System. The SoPC system components page as shown in Figure 5, Figure 5 only provides part of the voice recording system components. Use SOPC Builder to generate a complete system, last generation programming files, hardware downloads, complete G.726 audio encoder in the SoPC design.

　　

　　

Because the DSP Builder Basic module in the DSP to algorithm-level description and Simulink graphical interface, so the design is very intuitive, top-down development processes.

Unlike traditional DSP development, greatly reducing the hardware DSP design created by the development cycle. Design of codecs can be used as the Nios II system peripherals, SOPC Builder conveniently integrated into SoPC system. At the same time, because the design is based on FPGA implementation of SoPC, so you can make design changes based on actual demand, on the system to be configured with a high level of flexibility. The G.726 Audio codec performance basically meets the design requirements