How can I reduce the RFID transponder design power

Portable design cost depends on several factors, not just the Silicon costs.

In fact, the cost of the chip manufacturing process (the complexity and maturity and yield) can generally be controlled by the circuit designers. As a rule of thumb, when it contains more than 1mm2, used for the application of RFID in supply chain costs begin to decline.

When RFID transponder from minimum to maximum range, its power is generally change 30 times, RFID transponder power requirements may have on the designers made a difficult to forecast.

Although UHFRFID transponder typical power available at the over 100 MW of magnitude, but the problem is not limited to power consumption. Even a short distance, you can provide enough power for responder may cause voltage overload. Transponder must work from-25 ° c ~ + 40 ° c in nominal terms, as well as from-40 ° c to + 65 ° c extended based on standard EPCGen2 temperature range.

Cost and power requirements greatly influenced on RFID transponder IC used in the production process.

As in previous series, Schottky contact RFID transponder design provides low turn-on voltage, low-capacitance and high current drive. In addition, it has been committed to adopt new technology, such as the BiCMOS and Silicon on Sapphire (SOS), it provides excellent performance with low power consumption. However, each method has its negative side. In CMOS technology Schottky contact was not regular, but generally require post-processing steps. Other techniques such as BiCMOS and SOS for most RFID transponder applications and too expensive.

Realizing low power circuit requirements of the other methods are dynamic threshold voltage MOSFET (DTMOS) technology.

It can take advantage of bulk Silicon CMOS technology to achieve low-cost production. Its full advantage is ideal for development of next-generation UHFRFID transponder, this article will detail on this. This article first describes the basic principles of DTMOS. Next, the digital, analog DTMOS and RF field implementation is important to note that this is because UHFRFID transponder include involving all three areas of the circuit. Finally, the presentation's meet EPCGen2 indicators UHFRFID DTMOS bandgap reference circuit chip implementation.

Basically, use of DTMOS belongs to the interconnection of wells and gate of MOS transistor (Figure 1).

For double well p substrate CMOS process, because only individual control and production of N-well, so this fact can only use P-DTMOS because N-p-trap with DTMOS to P substrate of common and low ohm pathway. However, N-type DTMOS can have deep N wells of technology. DTMOS's action is similar to weak inversion MOS action, similar to the lateral PNP transistor operation in the tube. Weak inversion MOS transistor leakage current and lateral PNP the collecting electrode electric current (in the saturated zone) to:

Where: F = FBJT = VBE.

For transistor, F = FWIM = [(VGS-VT) × COX (COX + Cdepletion)]

Used in weak inversion MOS transistors.

Depletion layer capacitance value depends on the width of the depletion layer, which in turn depends on the well's doping characteristics, as well as Silicon source extremely junction voltage drop in the vicinity.

Therefore, this factor depends on the well-source voltage and modulation effect through the threshold used by the well-to-source voltage.

DTMOS can be considered as base has additional grid horizontal bipolar PNP.

Based on this perspective, the leakage current DTMOS depends largely on the trench by sources — in the voltage VGS and ID between an ideal index (similar to double pole). As a result of interconnection grid — well, at the gate and well between built-in voltage FGW. As a result of the distribution, voltage capacitor FGW in gate oxide and Silicon was once again assigned. This means that the voltage drop in Silicon as the FGW as barrier, lower voltage Fb1, DTMOS of leakage current can be expressed as:

Derived from these key findings are as follows:

1. Silicon pn junction 1.2V DTMOS devices than the band apparently 0.6V;

2.DTMOS devices have an ideal index characteristics [IDaexp (qVGS/kT)];

3.DTMOS devices with transverse currents exp (qFb1/kT) factor, it is usual to lateral PNP;

4. band gap voltage temperature dependence with the obvious.

Use of the production process 0.25umDTMOS successful design work in 77K temperatures, use 0.6V power supply voltage and the substrate to fixed to the bias voltage. The next test including managed grid horizontal bipolar transistors (GCLPNP) and substrate is connected to a gate-silicon insulator (SOI) MOSFET technology. The first technology to small low-power analog application, while the second process is typical of ultra low-power CMOS technology the best candidate.

DTMOS technology in the gate-delay/power connection and traditional CMOS technology showed incredible performance advantages.

DTMOS also in RF Circuit shows superior performance. In the tradition of CMOS, down to smaller feature sizes and threshold voltage (VTH) technology has increased the speed of work. However, the lower the VTH has also led to subthreshold MOSFET behavior. Static circuit quiescent current increases, the VTH limit 0.4V. DTMOS may can overcome these constraints, in particular work with steep subthreshold of extremely low VDD and low VTH. Transmission of DTMOS, gateIn voltage to the bias the substrate, according to the famous body effect formula, VTH reduces: