By FPGA audio sample rate conversion

Today, even in low-cost FPGA can also provide far greater computing power DSP.

Current FPGA includes a dedicated DSP multiplication/multiplier even (MAC) module add up to more than 550MHz clock speed of processing the signal.

However, until now, the audio signal processing also seldom need to use these features.

Serial implementation kHz-level audio algorithms use of resources and hundreds megahertz level signal processing necessary to exactly the same.

Therefore, like the PLD and FPGA programmable logical components of this kind is rarely used to handle the low-frequency signal.

After all, and based on traditional DSP implementation compared to hardware parallelism mathematical operations unprofitable at all; for such a low sampling rate, most serial DSP is more than adequate. In fact, the audio application contains more than multiplication has so that they can only use very large FPGA. Therefore, with DSP low sampling rate audio application once than to use more efficient large-scale FPGA — lower costs, but also a sophisticated software support.

Synplicity Synplify company recently launched DSP synthesis tool will have a large number of multiplication and the low sampling rate algorithm effectively mapping to FPGA DSP module in private.

The tool is based on the MathWorks company launched the great popularity of MATLAB and Simulink tools.

Algorithm to use a dedicated set of modules or proprietary "M" script language definition, and then converted to RTL hardware description language.

This module sets allow single-rate and rate achieved. Not only does it generate VHDL and Verilog code, can also handle fixed quantization, line and loop expand such tasks, and can connect to Simulink development environment simulation module Assembly (see Figure 1).

　　

Figure 1: in MATLAB/Simulink implementation, quantification in and verify that model.

Synplify DSP tool will models converted to RTL code for space or speed on these code optimization.

Application example: sample rate conversion

The following spoke in the audio sample rate converter for instance.

This converter can signal from one sample rate conversion into another sampling rate, and the effect of the signal. Dealing with a different sample rate of the signal requires this kind of converter.

For example, a CD of the sampling rate is 44.1kHz, digital audio tape of the sampling rate is usually 48kHz.

Due to data format conversion, use new sampling rate playback source data is not enough. To digital audio tape using sampling rate playback the disc information will cause distortion. Therefore, you must convert the sampling rate to be.

Processing of audio signals with sampling frequency has multiple, common 44.1kHz, 48kHz, 96kHz and 192kHz.

The conversion process must be careful, be sure to keep 0-20kHz audible frequency signal integrity. Should maintain signal changes in the information contained in the smallest decline, so that the sound quality (Figure 2).

　　

Figure 2: using the Synplify DSP module sets and Simulink FDA tools provide modules for sample rate converter.

Using Simulink module assembly components for validation.

Obviously, using FPGA implementation of audio frequency of sampling rate converter has the following problem:

1. the algorithm of problem:

A. the highest possible signal to noise ratio

B. the information contained in the original signal possible minimum changes

C. algorithms described as FPGA resource consumption in the depends to a large extent on the quality of the description

D. quantization

2. implementation issues:

A. logic correct algorithm implementation

B. FPGA resource limits

C. speed optimization implementation

D. deferred

Conversion require higher clock speeds, because the concrete realization depends on the conversion of signal oversampling of enough.

FPGA system clock frequency and signal frequency conversion differences must be larger.

FDA tools can help generate and verify a variety of FIR and IIR filters.

The tool is Simulink signal processing toolbox components, Synplify DSP is using this structure implements the filter Toolbox

For CD-quality audio signals, but also not less than 100dB signal to noise ratio.

Professional application of even greater than 120dB of audio signals. The signal quality, other low frequency signal (such as a control circuit algorithm) is far better than audio signal so harsh.

Algorithm

Multiple-phase FIR filter structure need to convert the sampling rate (asynchronous resampling).

Algorithm including two steps, the first step is the frequency of oversampling, the second step is linear interpolation, this is generated from the given frequency in different frequencies. These two frequency are asynchronous.

To single-step mode signal resampling the desired resource, because the filter will be more complex.

This implementation requires millions of times a multiplication. This description is inefficient and should be avoided. If the linear interpolation in a second step, the structure is much simpler (Figure 3).

　　

Figure 3: two steps to achieve sampling rate converter (a, oversampling, linear interpolation) to enhance efficiency.

Efficiently describe oversampling (first step) is to allow the FPGA implementation of a unique method of saving resources.

If you use a number ofCascade-class instead of a single operation steps to implement this part of the circuit, the required number of operation would be significantly reduced.

In algorithms, you must determine the implementation of the operations of the target schema (DSP or FPGA).

And has a fixed structure of digital signal processor, FPGA enables any schema. However, when you implement a large number of separate multiply, FPGA devices will eventually be affected by the size limit.

The number of the desired multiplier will increase as the filter tap.

Each tap needs to use a DSP module or multiplier. When cascading resampling circuit, the filter must perform complex functions of the low level. In theory, the more individual level, the filter for the better.

Reduce the number of operations of the methods of Mathematical derivation in technical literature has been widely discussed in.

Practice shows that while it was necessary to cascade filter circuit, but must be on the cascaded count limit. If you use a cascading series too much, you might exceed the resources available to implement the design. If you use the FPGA target schema, practice has shown that the best two-stage circuit.

The entire circuit for oversampling two relatively simple filter and a simple linear interpolation for composition.

This structure can effectively mapping to the FPGA.

Design implementation

You can use in Simulink Synplify DSP module sets and Simulink for filter design and analysis tools (FDA) for the circuit.

FDA tools can help generate and verify a variety of FIR and IIR filters. The tool is Simulink signal processing toolbox components, Synplify DSP is using this toolbox for filter structure.

Synplify DSP module set or all FDA tools provide circuit elements in PortIN and PortOUT description between defined, they can generate VHDL or Verilog code.

Simulink module set FFT and SCOPE elements on dynamic response spectrum analysis and validation. These modules are designed for functional verification, including floating point to fixed point conversion function (quantitative). These modules are not hardware implementation.

Realization of the first part includes two FIR filters: first filter 512 tapped, the second filter by 64 tapped.

Therefore, the generated by oversampling RTL code total multiplication with 576, this is what appears to be using FPGA and not with commercial viability. Such a large FPGA was cost constraints, because you need to have 640 DSP48 module oversize Xilinx Virtex-5 XC5VSX95T devices.

Is not mapped to a dedicated hardware structure (DSP module) multiplication of all must use generic logical resources (LUT or register).

This will lead to increased resource requirements and maximum clock speeds to drop. Compared with common logical unit, dedicated DSP48 module as multipliers will be much more effective (Figure 4).

　　

Figure 4: Simulink for filter design and analysis (FDA) tool for filter.

Design optimization

Synplify DSP folding options to minimize the number of the multiplier.

In the low sampling frequencies of circuit especially from this optimization.

Its principle is simple.

Typically, each multiplication using a hardware multiplier, even though for kHz sampling frequency level. However, the FPGA can be several hundred megahertz level clock speed. If a hardware multiplier in FPGA system frequency, you can use time multiplexing process sequence processing multiplication on time.

Assuming that the circuit of the sampling frequency is 3MHz, and FPGA Supreme can run under 120MHz frequency.

If you run the system frequency multiplier, each hardware multiplier can perform 40th operations. At this point the hardware can be reduced by 40 percent. This means you can add the sample rate converter (or use low sampling frequencies of any other circuit) "collapse" to only need very little hardware multiplier. Therefore, you can also minimize the existing low cost FPGA in implementation of this converter, thus truly replace DSP.

Of course, also possible to calculate the amount of the special big algorithm from the DSP FPGA, thus reducing the load on the processor.

If your application has exceeded DSP performance limit, and you have to target specific DSP application source schema into heavily, then this method is especially useful (Figure 5).

　　

Figure 5: you can use the collapse feature significantly reduces the required FPGA resources.

Because the Synplify DSP in the collapse feature also supports multiple rate system, and only a sampling frequency of the system, you can further reduce the number of the desired multiplier.

Oversampling used two FIR filters. The two filters to run different sampling frequency. The higher the sampling frequency can be used to run the filter you specified collapsed collapse coefficient.

A low sampling frequencies filter with relatively high coefficient of collapse.

This coefficient is used two filter sampling frequency difference multiplied by the coefficient of folding. For example, if a filter sampling frequency is another filter 8 times, faster filters used factors 8 folding, and a slow filter coefficient 64 collapse.

This may even be generated to usually cannot collapse of very high sampling rate of space optimization circuit.

For example, if the system to run 200MHz sampling rate and use the folded coefficient 2, then the system frequency will increase to 400MHz。

You can also collapse the coefficient is defined as 1.

To the maximum sampling rate running circuit elements do not collapse. However, to a lower sample rate operating system of all circuit components are available from collapse and space optimization implementation. You only need the system as a whole to its definition collapse coefficient can be. Then, the collapse will automatically propagate to all the sampling frequency.

You can put the collapse feature and another optimization feature-heavy timer function.

If your system does not meet the requirements of the target rate, you can increase the line series, until you achieve the desired speed. This approach is to use high folding coefficient of circuit is particularly important, because this type of circuit requires a relatively high system speed.

You can collapse the little or no collapse of the circuit using Retiming, unless you have reached the limit of the FPGA.

You can increase the line series to reduce two register combinations logic gate number (logical progression), which may improve system clock speed.

In the generate RTL code, Synplify DSP tools for time-series analysis, it will consider the desired sampling frequency, folding coefficient and FPGA target schema.

For example, in a slow, low-cost Spartan-3A DSP FPGA in exactly the same circuit, you can use fewer lines series optimized map to quickly Virtex-5 FPGA circuit.

You can use a large number of registers available FPGA for this optimization.

Register to use the multiplier or LUT (look up table) that will run out soon, which means that you can use the register easily to significantly improve the speed of the system clock.

Of course, increase the line series will increase system latency.

For example, if you use the reset timing factor 8, calculation result will later eight system clock period (not a sampling frequency cycle) appear in the output of the FPGA. To embed circuit system must take this into account (Figure 6).

　　

Figure 6: you can use the reset timer function for circuit definitions allow the maximum delay.

And then the Synplify DSP auto adds line series, until you achieve the desired frequency.

In particular, it is important to ensure that the above optimization does not affect the original described in Simulink MATLAB model.

Validation can be carried out on the algorithm, and to quantify the identification of effects to expressive. Synplify DSP software module set allows you to use truncation (remove unrelated bits), rounded (underflow) or saturation (in overflow cases) from floating point to fixed point conversion. Once the simulation shows the algorithm works correctly, you can generate RTL code. Optimization of VHDL or Verilog code might change the delay, but does not change the circuit.

A brief summary of this article

Synplify DSP tools based on the MathWorks company launched industry standard MATLAB/Simulink software.

Module set to provide standard component library can be used to implement complex algorithms. Apart from the addition, gain and delay, and other basic components, the library also contains FIR or IIR filters and many other complex features and CORDIC algorithm. All features (including the highly complex FFT or Viterbi decoder) can be arbitrary parameterized. You can also create user-defined library, or add an existing VHDL or Verilog code integrated into the Simulink model.

Use the Synplify DSP can implement single-rate and Multirate systems.

Use the collapse, multichannel or heavy timer function can be tailored to the size or speed optimized code. Generated RTL code is unencrypted common code, you can use common tools for integrated.

In order to achieve the best results with FPGA, Synplicity Synplify Pro recommended comprehensive tool.

At present for ASIC development environment has also been launched.