Summary: in the study of the reader and RFID tags on the basis of the communication process, combining EPC C1G2 Protocol as well as ISO/IEC18000.6 agreement, the use of VHDL Design a UHF radio frequency labels of digital circuits.
On the circuit of system structure and module implementation methods are described. Based on 0.18 μ m CMOS technology standard cell library, using EDA tools for integrated circuit for the front-end and back-end physical implementation. The simulation results indicate that the circuits in compliance with the agreements, the integrated circuit scale after about 11000 door, power consumption of about 35 μ W. The circuit can be applied to a variety of UHF RFID tags section of the digital part.
1 Introduction
Radio frequency identification (RFID) technology as a new kind of automatic identification technology, both at home and abroad in recent years has been rapid development.
At present, China's development of RFID products generally low frequency-based, such as the second-generation ID card, ticket management. In the UHF segment our homegrown products less, making it difficult to adapt to the huge market demand and intense international competition. Ultra-high frequency (UHF) label refers to the operating frequency in the 860 ~ 960 MHz RFID tags with read/write long distance, reading speed, scope broad, etc., can be widely used in logistics management, storage, access control, etc. In order to meet market needs, this article to EPC C1G2 agreement, ISO/IEC18000.6 supplement, designed a UHF labels of digital circuits.
2 UHF RFID tag works
Radio frequency identification systems are typically determined by the reader (Reader) and RFID tag (RFID Tag).
Attached to the question to identify objects on the RFID tag memory agreed format for electronic data, as the question to identify items of identifying information. The reader can read labels with no contacts in the electronic data or information is written to the tag, in order to achieve the object of the automatic identification and management. Reader and RFID tags in accordance with the conventions of communication protocol using advanced RF technology to communicate with each other, their basic communication process is as follows.
(1) the reader role within the label carrier receiving reader sends energy, power-on reset;
(2) label receive reader sends commands and operations;
(3) the reader choose and inventory order issued on label identification, selected a single tag to communicate, the remaining labels temporary dormant;
(4) unrecognized tags perform Reader access to the command is sent, and inverse scattering modulation mode sends data to the reader, to sleep, then no longer answer to the reader;
(5) the reader to the remaining labels continue to repeat the search, (3)
(4), respectively, wake-up a single label for read until identify all labels.
3 UHF RFID tags with structural and system specifications
UHF RFID tags in the diagram shown in Figure 1, from analog and digital made up of two parts.
Analog circuit including antennas, wake-up clock generation circuits, circuit, envelope detector circuit, circuit and reflection modulation circuit; digital part of the main implementation of EPC reader communication protocol, to identify and execute commands, such as when reading multiple labels anticollision method, perform the reader sends a read/write command, the realization of the reader and the tag's communication process and output data as encoded. Agreement provides for labelling system specification as shown in table 1.
4. the label design of digital circuits
4.1 circuit design of the overall system
After the contents of the agreement, this article takes an in-depth study of design method, Top.down first circuit features a detailed description, in accordance with the functionality of the entire system for modular Division; then a hardware description language VHDL RTL code design and functional simulation; function correctly after using EDA tools, process library optimized for logic synthesis; and finally uses the automatic layout wiring for formation of chip layout design.
This article determines the structure of the system diagram as shown in Figure 2, which includes decoding module, CRC (cyclic redundancy check, a cyclic redundancy check) calibration module, state machine modules, CRC generation module, memory, encoding module and clock frequency module. Decoding module receives analog demodulation of command signals, in accordance with the agreement of command format will signal decoding a tag number portion of the recognized binary data, and send it to the CRC modules and state machine modules. CRC modules to command the integrity check, if recognized as a valid command, the trigger state machine modules, control tab to perform operations such as read-write memory, anti-collision control, etc. When processing is complete, the data will be sent to the CRC generation modules produce the appropriate CRC checksum, and then will be sent together with the data and parity-check codes sent to encoding module, the module by coding to a specific form of pulse is sent to the analog part for processing and use of radio frequency technology to the reader. To reduce power consumption, the clock frequency module for global clock frequency, the frequency of frequency can be used by other modules using the digital part. Memory storage labels identifying information. The following will describe the implementation of the various modules.
4.2 decoding module implementation method
The command takes the reader to issue PIE (pulse.interval encoding) format, in order to synchronize the head (preamble), as shown in Figure 3.
Decoding module implementation method: first judgment on the first synchronization, the labels for the input signalDetection, once detected falling edge description may be a new command delimiter (the delimiter), count low level, will count values stored in registers count0, simultaneous detection of the input signal is a rising edge jump to jump on the rise, the data is cleared to zero recount and after the count value delimiter into register count, continue to compare registers the value of the count count0 and, as shown in Figure 3, figure out the relationship between the delimiter, data 0, RTcal (reader to tag calibration), TRcal (tag to reader calibration), confirm the synchronization of the head; and then synchronize the data after the head than RTcal/2 short as data 0, than RTtcal/2 long as data 1, from a range of high and low level of recovery of the real 1 signal and the signal, 0 into the command registers, and provides the control state machine and validation module related flags.
4.3 CRC checksum generation module
UHF RFID system uses a cyclic redundancy check (CRC) to determine data validity and integrity, CRC can protect reader of RjT (reader to tag) command and inverse scattering of TjR tag (tag to reader) sequence.
From a mathematical point of view, the CRC is used will be processing data bytes as a binary polynomials coefficient of A (), the coefficient is divided by the sender and the receiver predetermined good generated polynomial g (), you will find the remainder of the P () as CRC. CRC calculation includes to calculate the CRC value of the data bytes, as well as all previous data byte CRC value. When a block is transmitted, the data sender computes the data block of the CRC and check code attached to the block of data transmission together after. Data receiver computes all received data CRC values, the result is always zero, or during the transfer process must transmit error occurred. Zero calibration can easily analyze data integrity and avoid costly checksum comparison process. Agreement with linear feedback shift register for CRC checksum, CRC.5 CRC.16 validation of circuit diagram shown in Figure 4.
4.4 RF tags in state machine
RFID tag all actions are based on a series of logical control state transitions, such as the label in the core of digital circuits.
This design uses finite-state machine to enable this module here uses three types of basic operations and 7 typical State. As shown in Figure 5, when you receive a different command, the label will be in 7 State between conversions. Select (select) command and inventory (inventory) command is used to identify from the label group a specific one, label the corresponding status is ready, arbitrate, reply, acknowledged; once the label is recognized, the reader will be issued access (access) orders, read the label of information or send information to the label, the label of the corresponding status is open, secured, and killed.
Identify multiple tags with stochastic precipitation tank anti-collision algorithm (slotted random anti.collision algorithm) to resolve the conflict.
Reader to read and write to the scope of each label sent contains parameter Q (a value of 0 to 15) of the Query command, the control label to their respective precipitation tank within the loaded a counter Q value of random numbers (range 0 ~ 2Q.1), random number generation is mainly based on linear feedback shift register. The reader then issued other inventory command to change the value of a random number, random number only when a value of 0, the label will not be answered. If multiple labels of the counter value is 0, these tags at the same answer, causing a conflict. The reader after a conflict is detected, the command issued inventory labels for conflict from random numeric value 0000h (hexadecimal) to 7FFFh, and then set the new Q parameter to random hash decomposer counter values, making the conflict more tags individually identified, keep an active tag and reader creation impact communication, thus effectively resolved the conflict. Although this method of distinguishing linearity (215_1) than binary search method (2 septentrionalis) low, but high reading speed, calculus, prevention mechanisms complete several signal collision possibilities, significantly reduce the probability of collisions of the signal.
4.5 coding module
Tag backscatter to reader data using FM0 coding, Figure 6 shows the encoding format. FM0
FM0 encoded data before a previous synchronization code, choose the former synchronous code from the reader's command of TRext parameters; FM0 coding in each data boundaries reverse phase and in the middle of reverse phase 0 data.
FM0 coding with memory function, a series of signal, after a level you must accept the end level on a bit, so you will need a register contains a bit on the end level signal, thereby to judging the next signal starting level. According to the reader's command to determine the label returned data link frequency (LF: link frequency), the internal clock count produces the required frequency as label returns data send rate. To reduce power consumption, you can set the global clock frequency, the lower the clock frequency. In order to correctly implement encoding functionality, you need to fully understand the standard, based on the strict definition of the module with the state machine interfaces betweenSequence. Encoding module only state machine module in the sequence on the close coordination, both sides to properly send and receive signals. Realization process: when the state machine sent makes can signal when encoding module effectively into the encoding status, while the state machine to send out the data signal; encoding module is triggered after the start, first of all, in accordance with the agreements before synchronous code, then you want to output the data then click encoding, resulting in a level 1 bit half 0 signal, or harmonization level 1 signals, serial; when the state machine to send the last bit of data at the same time, notification encoding module, state machine data has been sent.
4.6 memory and storage control logic
RFID tag data information is stored in the storage, general use EEPROM to store EPC code and password, and other labels identifying information.
Memory and state machine interface 5 J: Di is memory input data signal; Do is store output data signal; Addr is memory input address signal; oen is output enable signal memory, high level of effective; cen is the memory chip, enabling effective signal, high level; we are the memory read/write control signal, we write valid = 1; when reading we = 0.
5 simulation results and layout
This article uses the VHDL UHF RFID tags were completed for digital circuit design, RTL code on the tag and reader communication process for comprehensive simulation and emulation, and is based on a 0.18 μ m CMOS technology standard cell library, the EDA tools used on the integrated circuit for the front-end and back-end physical implementation.
The simulation results as shown in Figure 7, you can see, the integrated circuit will reader after issue of the format command CMD data PIE succeeded in decoding the binary data, stored in command register command and in control state machine and validation module related commands enable signal (Query QueryAdjust — en en, etc.); in various commands enable signals triggered by label do, according to the reader requires all output data (rn, handle, and so on); and the output data encoding generated CMD out FM0; also implements the interface with the memory. Simulation results show label digital circuit in various situations are functioning, fully meet the agreements. Integrated circuit scale after about 11000 door, power consumption of about 35 μ w. Because the circuit is very large, through automatic layout line layout design, the design of the layout shown in Figure 8. Empire has passed the DRC (design rule check) and LVS (layout and circuit diagrams are consistent comparison) authentication, time-series analysis also suffice, the circuit has a large margin, higher reliability.
6 closing
This article is based on EPC C1G2 and ISO/IEC18000-6 protocol, use of VHDL Design and EDA tools for UHF RFID tags for digital circuit that can be applied to work in a variety of UHF RFID tags section of the digital part.
The article gives the simulation results indicate that complete the design consistent with the agreements. Logic synthesis also get satisfactory results, ensure the circuit of high performance and back-end design with a smooth finish. Later work is the result of convection film, also to be tested, in meeting the agreement on the basis of the functional requirements, how to simplify the circuit structure as possible and minimize the power consumption is a further research.
