Video monitoring system in the multi-screen processor design (1)

In recent years, as the video surveillance system in all areas of the widely used as video surveillance, one of the last system composed of multi-screen processor of increasingly widespread.

Such as the use of a nine-screen processor, you can in one monitor simultaneously monitoring nine goals, just use a VCR will be on the road video signal at 9 real-time video. Currently, multi-screen processor has a black and white/color 4, 9, 16 6 picture processor, etc. In General, multi-screen processor in addition to the image segmentation capabilities, with video signal switching and alarm functions. Video signal power swap function is a multi-screen processor has one channel video output is the input video signal or screen split signal sequence to switch, and switching time adjustable; alarm function is a multi-screen processor can input and output alarm signal, alert the appropriate screen overlay with alarm message and alarm information stored for future reference. Design of multi-screen processor can use dedicated DSP chips, although satisfying the requirements of the speed, but the longer development cycle, product testing, modifying and upgrading difficult, costly. Due to the FPGA (field programmable gate array) devices with high integration, small size, low power consumption, design flexibility and lower prices, fast and efficient development platform to accelerate development cycles, and other advantages, multi-screen processor design is basically using FPGA as video signal processor. Due to the FPGA features from its internal programming data determine the programming data loading method is one of the following power-on-chip implementation, multi-screen processor with MCU. On the one hand use after power-on-chip in the FPGA required programming data written to the FPGA, on the other hand video signal switching, OSD and alarm information processing is accomplished by the SCM. The following specific presentations based on FPGA and SCM black and white four pictures processor design methods.

1 black and white four pictures processor main features of the composition and

1.1 black and white composition of the four screen processor

Black and white four pictures processor block diagram shown in Figure 1.

We know from Figure 1, the multi-screen processor to FPGA devices and microcontroller core, plus A/D and D/A, frame memory, serial memory, serial clock and OSD, companion chip.

1.2 black and white four pictures processor main features

The main function of four pictures processor as follows:

· Video format for CCIR modes, the video signal field frequency 50 Hz;

· Duplex operation (while the video is available for playback), menu settings;

· Full-screen display pixel to 1024 × 512,256 grayscale;

· 4-channel CVBS input and 1-channel video input;

· 1 full frame and quad switch output, 1 video output (fixed 4 segmentation);

· Switch time adjustable range 1 ~ 255s.

· Screen can overlay time date and position can be adjusted;

· There is alarm input/output functions, alarm reset time adjustable range 1 ~ 300s;

· Video signal loss alarm function, alarm time corresponds to the text displayed on the screen.

2 sections circuit structure and working principle

2.1 input buffer and A/D conversion

The part of the circuit's main function is the input analog video signals into digital video signal processing for FPGA, the block diagram shown in Figure 2.

4-channel video signal is simulated by FPGA control multiplexer, output 2 channel video signal, after buffer amplifier evacuation to FPGA-controlled analog switches; and then output to the A/D, 2-channel video signal requires 2 tablets A/D chip. A/D chip selected TLC5510, the chip is a resolution of 8 bits, 20MSPS (20 MHz sampling points/second) CMOS die/number converter. Under the control of the FPGA, TLC5510 will enter analog video signals into digital video, and then sent to frame memory.

2.2 frame memory

Frame memory selected AVERLOGIC company AL422, 2 slices were needed.

AL422 is the storage capacity of 384KB×8Bits FIFO (First In First Out) DRAM, and it supports VGA, CCIR, NTSC, PAL and HDTV resolutions, with separate read/write operations, and output enable control; storage time 15ns high-speed asynchronous serial access to 5V or 3.3V power supply voltage, Standard SOP package of 28 feet.

2.3 FPGA devices

FPGA is the core of this design, and the traditional logic circuits and gate array in comparison with a different structure.

FPGA using small lookup tables (16 × 1RAM) for combinational logic, each lookup table connected to an input D trigger, the trigger and then D to drive other logic or driven I/O. These modules use metal wires connected or connected to the I/O modules. FPGA through to internal static storage unit load programming data to achieve its FPGA through internal static storage unit load programming data to realize its logical, stored in a storage unit value determines the FPGA function; FPGA this structure allows infinite reprogramming. Thus, using FPGA design product modifications and upgrades are debugging is easy, and with great flexibility. There are many kinds of FPGA, in this design choice of Spartan series XCS05XL. The chip is a Xilinx company launches low-price, high-performance FPGA, whose main characteristics are as follows:

· The system has reached the door, 5000

Logic cell number reached 238, system resources;

· Distributed with on-chip RAM, programmable maximum programmable RAM up to 3200bit;

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