Use LVDS buffer overcome high-speed signal path resistance is not continuous challenges of

For more than the rate of the signal 200Mbps, if you omit the parasitic resistance and impedance discontinuities, will increase in the transmission of noise on the produce, and a data bit error.

This article will be the basis of high definition digital video router is treated as an example, a detailed explanation of these issues.

When a data transfer rate is between $ 1.5Gbps 400Mbps, signal path (signal path) is into the transmission line (transmission line).

The transmission speed, signal path model must include cable or backplane of reactance of parasitic components. High speed data transmission problems not just data transfer rate itself, fast signal edge transformation rate contains even more high frequency components, these high-frequency components in distributed impedance transmission performance in your environment. For more than the rate of the signal 200Mbps, if you omit the parasitic resistance and impedance discontinuities, will increase in the transmission of noise on the produce, and a data bit error.

Examples of high speed signal transmission

Faced with this problem, we at HDTV Foundation (High-Definition, HD) digital video router is treated as an example for illustration.

HD video router can be managed from broadcasting, Studio or programming device between the various sources of data streaming HD programming. HD video pipeline is up to 270Mbps 1.485Gbps rate range operation, it needs to be carefully designed and adopt a consistent design method to ensure that the Exchange Router system does not reduce the integrity of video information.

　　

　　

Figure 1: high definition video router diagrams.

In Figure 1 of this system, you can adjust the equalizer (EQ) received directly by the BNC connector on the HD signal.

A common backplane will signal from input card connected to a switch card, to output to the target signal. Signals from the EQ after nearly 8 inches of PCB, point-to-point transmission backplane connector, and then through 3 to 15-inch backplane (length depends on the type of socket) to the second connector, then after eight inches of PCB to Crosspoint Switches component input. A reorganization, smart (re-clocker)/cable drive connected directly to the output of the Crosspoint Switches to drive signal transmission in cable. These HD video router system is modular, may have 8 to 1000 input/output signals in the pipeline. Also because of this, signal density can be very high.

　　

　　

Figure 2: signal path impedance TDR figure instance.

FR4 circuit board materials in General belongs to the impedance of a consistent environment, but distributed parasitic impedance on signal quality will have a negative impact.

Some of the greatest effect, because a lot of work in the information above the basic rate of frequency components produced by the rapid rate of upper and lower edges of the transform, the signal loss and slow conversion time. In addition, the component (for example, BNC connector, of circuit, circuit board aisle between the different layers, or Board hole between the connectors) of interconnected may cause and characteristics impedance (Z0) impedance mismatching, this also affects the signal quality (fig. 2). Intensive backplane connector will increase for the signal path, and the inductive load PCB aisle hole increases the signal path of capacitive load.

In signal transmission path, any changes place exists impedance may appear signal reflection.

These reflection and parasitic impedances will result in a loss of signal amplitude, circular wave, rise time gets longer and EMI. In this example, the output from the EQ to Crosspoint Switches input length is expected between FR4 circuit board 31 inches long, in the path H appears several resistance is not continuous. If you go down this path of incident edge (incident edge) speed of 175 to 200 ps/inch, data rate as 1.485Gbps (half-wavelength = 343 ps), at any given time there are as many as 18 pass edge. Impedance mismatch of reflex incident edge, will affect the signal path on the edge of all signal transformation. 1 from the signal edge to signal edge 17 reflection reaches the signal path Terminal, will enable the 18 signal edge severely distorted. The result is eye-diagram (Figure 3) displays the amplitude loss, jitter, and the rise of additional/fall time changes.

　　

　　

Figure 3: after 31 inches of FR4 circuit board transfer, Crosspoint Switches input at the eye-shaped figure.

　　

Enhance the quality of the signal transmission

For the challenge of a solution is in the daughter card and backplane connector with high quality, which will enable the continuity of the connector.

Better design of the gangways hole will further enable TDR measurement diagram flat, this will make the length of the signal path of actual impedance Z0 will and is very close.

In addition a more cost-effective solution is to use a simple LVDS buffer to drive and receive the signal on the backplane.

It will signal transmission path and then broken down into short segments to shelter impedance mismatching of problems, and reduce the signal attenuation.

At the edge of the card by placing a buffer to drive connector and the floor, then through the exchange of the daughter card in addition to a buffer that receives the signal (Figure 4), and then reinstall the driver for these signals to the input Crosspoint Switches to effectively hide the two buffers between resistance is not continuous (Figure 5).

The correct impedance termination will be in a position to ensure that the receiver absorption lines of all the energy that makes these signals will not be reflected back to the source client.

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Figure 4: use buffers to overcome impedance discontinuities.

　　

　　

Figure 5: using buffers isolating backplane connections after the intersection at enter eye-diagram of the signal.

In addition, buffers are often also can enhance signal quality, improve the original signal.

For example, with input Equalization of bumpers in the backplane signal transmission medium loss brought before the Elimination of quantitative jitter (deterministic jitter). Output has increased the functionality of the advance signal to increase the signal range, making the intersection at enter or receiver eye-shaped figure more open. In buffer I/O, High ESD limit protects the daughter card other components from other locations on the backplane of the ESD incident occurred.

　　

LVDS buffer function

The following will be a four-channel LVDS 1.5 Gbps buffer/Repeater for example.

The components of high speed data paths and through PIN makes the symbol internally generated jitter and simplifies PCB design. It can be configured in advance to strengthen the signal function, you can overcome the backplane and cable losses brought about by the ISI jitter effect. Potential difference to input and output in an internal 100 Ω termination resistors to improve performance and reduce the size of the Board. Enhance the signal strength of a Repeater function for in high losses in cable and backplane signal long-distance transmission, particularly useful.

　　

　　

Figure 6: a four-channel LVDS 1.5 Gbps buffer/Repeater typical applications.

LVDS buffer has charged docking protection and electrostatic discharge protection 15kV, can strengthen the backplane and cable anti-interference ability, can guarantee field programmable arrays (FPGA) and exclusive product block circuit (ASIC) transmission of signal integrity.

Its applications include telecommunications, data communications, industrial systems, medical equipment, automotive electronics systems and Office image system, typical application shown in Figure 6. LVDS buffer can, through common backplane or simple cable configuration-driven four LVDS clock and/or information channel. Because of this poor wafer bit wide input voltage range, it is acceptable to LVDS, low voltage positive emitter coupled logic (LVPECL) or current-mode logic input level, output level fully compatible with LVDS specifications.

As an example of LVDS buffer chip data transfer rates up to 1.5Gbps, and system design engineers can use this chip configurable output pre enhancements will output to "enhancing driving force" in order to be prone to signal loss interconnection circuits provide compensation.

In addition, you must try to conserve electricity application (such as redundant applications), and four of the chip are suspended operation system through a low-power mode power consumption to a minimum.

Summary

Across the backplane of the high-speed interface needs throughout the entire signal path control impedance.

LVDS buffer used sample profile at main level to isolate resistance is not continuous or shortening the length of the Internet can reduce system costs; and also because there is no need to use high cost of high-frequency connectors, further enhance the effectiveness of the operation of the interface.