USB 2.0 interface-based high-speed data acquisition system design (1)

In the modern electronic systems, signal detection, image processing, audio and video signal processing, such as high-speed, large-capacity signal acquisition and transfer process, data, real-time acquisition and real-time transmission is increasingly widespread attention. Now generic data acquisition card is a PCI card or an ISA card, the card there exist many shortcomings, such as the installation is easy, the transmission speed is slow, computer socket number, address, interrupt, and other resources. scalability.

LJSB (Universal Serial Bus), of which the Chinese name for "universal serial bus".

He is in order to address the kinds of computer peripherals and the limited increase of IK motherboard slots and end the conflict between d r., by Intel, Microsoft, IBM, lucent, NEC companies jointly developed by bus standards. At present, the usual LISB 2.O release supports the highest transfer speeds up to 480 Mb/s: and he to speed, low cost, high reliability, support for Plug and play and hot swappable, etc., prompt access to many PC manufacturers. At the same time, the development of this USB 2.0 high-speed data acquisition system, represents a modern data acquisition and transmission system, he will be more and more accepted by users.

The overall design of the l-system hardware

The overall framework of the system for the PC (USB 2.O Protocol can be supported by your computer), A/D conversion modules, FPGA control module, control modules, such as LYSB map l shown below.

　　

Overall structure can be divided into two parts: a high-speed data acquisition module Design; USB 2.O high-speed data transmission system.

1.1 data acquisition module

This system is mainly composed of l tablets high-speed AD chip, 1 slice of SDRAM and l tablets A1tera company of FPGA.

Because the system design of the sampling rate up to 1 MHz () 0. According to the sampling theorem, sampling frequency should be at least more so in 200MHz A/D chip uses Analog high-speed A/D chip AD9480. The chip conversion precision 8 b £ ® single 3.3 V power supply, low power consumption, maximum operating speeds of 250 MS/s, the use of differential forms, LVDS level output, after the test is a good way to meet the system requirements.

In order to meet the data collection in high speed application of real-time streaming data, avoid FIFO overflow, this system through the FPGA and SDRAM constructs a bulk of FIFO, can provide a low cost and can satisfy high-speed real-time streaming data transmission programme.

Low-speed data acquisition systems often use MCU control as a CPU, but in high speed data acquisition system, sampling rates tend to be affected by the impact of MCU speed, and with the speed increase, ADC, between the SDRAM and MCtJ timing synchronization issues are also displayed, so the system uses a high-speed FPGA chip to control ADC and SDRAM, which is a great way to solve the timing accuracy and synchronization problems.

FPGA choice A1tera company CYCLONE series high performance-cost ratio products EPlC6T144C8.

He, based on 1.5 O.3 μ m V-layer copper SRAM technology, its density is increased to 20 060 logical component (LE), RAM up to 288 kb. He has a phase-locked loop and SDR and DDR speed cycle RAM (FCRAM) memory required dedicated dual data (DDR) interface, etc. CYCLONE devices support a wide range of I/O interface standards, including 640 Mb/s LVDS, and speed of 33 MHz, 66 MHz and data width is 32 b and b PCI 64. FPGA implementation of the function logic: the control of the ADC, start A/D conversion; for ADC synchronization with SDRAM address count and write signal, each time A/D conversion results directly into SDRAM, and automatically add the address address; when the counter reaches maximum, issued RAMFULL interrupt signal that prompts the SDRAM is full.

FPGA function logic using VHDL, its compilation and simulation using Altera Corporation Q u a r t u s Ⅱ 5.1, use the B B y t e l a s t Ⅱ parallel programming cable and JTAG port download programming and configuration files.

1.2 USB 2.0 high-speed data transfer

For USB device development of chip, usually there are 2 types: one is integrated inside the chip MCU, such as CYPRESS's EZ-USB; the other is pure USB interface chip that only deal with USB communication, must be from outside microcontroller (MCU) for the control, such as Philips, PDIUSBD1 2 National Semiconductor's USBN9604, etc.

In this design after demonstration analysis, using the first type, using the Cypress company EZ-USB FX2 CY7C68013 chip series.

1.2.1 EZ-USB FX2 (CY7C68013) chip

Cypress company EZ-USB FX2 series chip is compatible with USB 2.0 Protocol microcontrollers, he integrates with USB 2.O Protocol transceivers (transceiver), serial interface engine (SIE), Enhanced 8051 kernel and programmable peripheral interface.

FX2 series chip unique structure allows data transmission speeds of up to 56 Mb/s, meets the USB 2.O bandwidth. CY7C68013 integrated standard 8051 kernel, and has the following enhanced features: you can reach 48 MHz clock; each instruction covers four clock cycles; 2 USARTS; 3 timer/counter; extended interrupt system; 2 data pointer.

805l program starts running from the internal RAM, use the following 3 ways to make programs load: download via USB, load from E2PROM; through the external storage device.

Internal integration of up to 4 kilobytes (KB) of FIFO, user program to send data directly from the FIFO, read to ensure that the high-speed transmission of data, and external implementation of transparent data transfer.

1.2.2 hardware connections

According to the data transmission speed and real-time performance requirements, configure the interface mode CY7C68013 work as Slave FIFO mode.

When conducting data collection, the hardware connections as shown in Figure 3.

A/D converter sampling clock at the same time as the Slave CY7C68013 F = IFO mode read/write control clock, i.e. CY7C68013 interface clock connection to IFCLK PIN.

SLWR/SLRD is CY7C68013Slave FIFO write enable/reading allows signal. FPGA to provide Slave CY7C268013Slave FIFO FIFO output allows signal SLOE, only valid when the data output. FD [15: 0] $ 16 b bi-directional data bus. FI-FOADR [1: 0] signals for endpoint FIFO choice. When in data entry, select a fixed endpoint 2 OO; data output is fixed at 10, ends 6.

　　

　　

　　

2 system programming

USB system software design can be divided into three parts: firmware design and driver design and client application design.

2.1 FW (firmware) design

Firmware is actually a SCM software design, he is all based on the micro-controller and peripheral circuit function devices to work correctly, the essential part of its role is to support the hardware.

[1] [2]