Multimedia Processor DM642 and video monitoring

Video surveillance system design there are many, but the mainstream market products generally a choice of two programmes: one is based on the CPU and a dedicated video decoder ASIC chip.

Select the programmes to ARM core processor, and dedicated media processing chip structures. Advantage is that development is relatively short, but because of poor ASIC, flexibility, and the products once stereotypes, it is difficult to change. The second is used for media processing, dedicated DSP. Its development time is not long, advantage is because the algorithm is software code, so you can continue to upgrade the product performance, repeat the development costs low. The world's largest manufacturer of DSP Texas instruments (TI) launched TMS320DM642 (hereinafter DM642) as a cost-effective, dedicated to multimedia application of DSP, has been a practitioner and foreign video application wide acceptance and adoption. This article is more detail about the main characteristics and DM642 system application development technology, and based on the video surveillance application DM642 instances.

DM642 multimedia processor

Is TI DM642 company specifically for multimedia applications and the development of the DSP, the use of TI's second generation advanced VLIW architecture (VelociTI) so that an instruction cycle to parallel processing instructions.

It can work under 600MHz clock frequency, each instruction cycle can parallel 8 32bit directive, therefore, you can reach the peak of the computing speed 4800MIPS. DM642 uses two level cache structure: first level including independent LIP (16kB) and LID (16kB), can only be used as a cache; the second level L2 (256kB) is a unified program/data space overall as SRAM mapped to storage space, can also be integrated as a level 2 Cache, or both the proportion of a portfolio. DM642 has 64 independent channel EDMA (extended direct memory access) controller and is responsible for on-chip L2 and the other data transmission between peripheral equipment. Larger two-level cache and EDMA channel is DM642 high performance includes, if reasonable use and management, will be able to greatly improve program performance. Its structure as shown in Figure 1.

　　

In addition DM642 rich peripheral interface, including three configurable dual-channel video port video port, where each videoport are divided into A and b, two channel, A/B channel can handle one channel video acquisition, therefore DM642 can handle up to 6-channel video acquisition data (without audio).

If the video port is configured to use for video output, you can only be used in A channel output, B channel cannot be, therefore DM642 can support a maximum of 3-channel video output (without audio). If you also handle audio, each video port can handle two-channel stereo. Also includes 64 external memory interface (EMIF), 10/100Mbit/s Ethernet MAC and multi-channel audio serial ports (McASP) and 66MHz32bit PCI interface.

The basic system consists of DM642 DM642 and spread of memory and peripheral components, and the spread of memory and peripherals are DM642 external memory interface (EMIF).

DM642 basic system needed to spread resources include:

(1) SDRAM (4M64bit) used to hold the procedure and cache digital video/audio data;

(2) FLASH (4M8bit), for curing procedures for ROM boot;

(3) UART (288bit), extended two asynchronous serial interface (RS232/RS422/RS485);

(4) Board register (n×8bit), consists of several 8-bit status/control register;

(5) hard disk interface (2816bit) for local mass storage interface.

Thus, DM642 is a powerful multimedia processor that can be used to achieve high-speed completed large quantity of digital video/audio codec processing, particularly suitable for the development of multimedia communication devices.

Is the current structure ideal for digital multimedia applications platform.

Application development technologies DM642

Software development tools

The company released by TI DSP integrated development environment for CCS (CodeComposer Studio), is a Windows-based DSP development platform, is currently the best and most popular DSP development software.

CCS integrates Visual editing interface can be directly written in C and assembly language, in addition to extend basic code generation tool, CCS also integrates C compiler, C optimizer, assembler, Assembly optimizer and connector, etc. And support for RTDX (Real Time Data Exchange) technology, which can be run without disruption to the target system, the implementation of DSP and other applications (OLE) data exchange. In addition, CCS breakpoint tool and probe tools and analysis tools enabling developers of all development processes are integrated in the CCS in this environment, including the establishment of the project, the source program to edit and compile and debug the program.

CCS internal also includes real-time operating system (RTOS) DSP/BIOS, primarily to multi-task real-time scheduling and synchronization as well as the host/target system communication and real-time monitoring of applications.

DSP/BIOS with real-time operating system for many features, such as the task of dispatching management, task synchronization and communication, memory management, real time clock management, interrupt management, peripherals-driven management, etc. Using DSP/BIOSTools can help developers more easily control DSP hardware resources, more flexible and coordinated implementation of the various software modules that accelerate software development and debugging.

DM642 a 256kbit/s-chip memory, for direct handling of image data is still very limited.

If at least MPEG-4 algorithm generally store the current data to be encoded frame and previous frame of reconstruction frame data, frame 2: YUV4: 0 format CIF image data about 150kB, 256kB, memory for CIF images are not enough. For DM642, data if placed on the Board outside the memory on the Tablet, the data processing speed is significantly reduced, this is because the DSP for tablets, data operations much slower. We usually take the programme is on the image to the macro blocks deal, only when the macro block operations need to import data from other data within the chip, to remain in the movie, this is sufficient amount of data placed on the chip.

Make full use of the DMA channel DM642

DSP directly access the memory will result in waiting, waste a lot of unnecessary clock cycle.

Fortunately, there are strong DM642 DMA capabilities so we can handle the current macro block data, the next macro block data from DMA into tablets, when processed the current macro-block, the block of the next macro data ready, which can greatly improve the utilization of the DSP. But the specific implementation of time need to start the timing of the DMA be carefully considered, in the data access without conflict as possible in advance.

Two-level Cache DM642

L1 and L2 formed a two-level cache DM642.

L1 distance DSP kernel more recently, data access is the fastest, just as a Cache cannot be addressed by the use of independent LIP and LID; LIPCache size 16kB, direct mapping, each row size for the Cache size 32B; LID, 2-channel mapping 16kB, each row size 64B. L1 and L2 is the external memory of middle-tier, larger capacity, 256kbit/s is a unified storage space, you can also store programs and data. L2 as SRAM mapped to storage space or overall as the second-level Cache, or as both the proportion of a portfolio mix. L2 as SRAM use, that is, on-chip memory DM642, from the entire system address space start address 0x00000000 start addressing, when used as a Cache, 4 road map, each row size is 32 128B, capacity in-between 56kB. In the actual development process to take full advantage of the Cache, the general principle is that as many key data distribution in the film, the larger the Cache, the better, for different applications require different configurations. Optimal configuration required in development based on experience and actual test results.

Video monitor instance

The following describes a network based on DM642 video surveillance system, as shown in Figure 2.

You need the following hardware: DM642, shoot like head, Philips company video decoding chip SA A 7115, Intel Corporation's LXT971ALC chip (PHY) and external RJ45, SDRAM and Flash memory. By camera acquisition of analog video signal SAA7115 ADCs, forming YUV4: 2: 0 format for digital video signals, from DM642 video port input; from software encoder based DM642 coding compression (software encoder can use H.263, H.264, MPEG-2, MPEG-4 and ranging M-JPEG existing or future video coding standards), encoding compression-generated video code stream data, packaged by RJ45 port via Ethernet to a remote destination, complete network video communications, and monitoring. By DM642 Mac interface, network transmission, video signals can be used by the video port 2 video coding chip-to-analog conversion output analog video signal to the monitor for local echo.

　　

The interface through the EMIF DM642, can be connected to the SDRAM and Flash memory (SDRAM extends the system's storage space available, system initialization and configuration information is stored in the Flash).

In addition to the video port DM642 through video decoder SAA7115 can easily implement and seamless connection of the camera, video port 0 and 1 respectively for two-channel video input, depending on your application needs, offers the flexibility to set up single or multi channel video input.

Closing remarks

You can see from the above description, DM642 is a powerful multimedia processor that is constituted of multimedia communication system with a good platform.

Its rich peripheral interface makes it almost is a multimedia embedded system of single-chip hardware platform; it's a fully programmable and can make it to a compatible is development, multimedia signal processing standards constitute a common software platform. These features will make it a wide range of applications.