Currently in highway, transit, electronic police, monitoring, security, industrial automation, electric power, customs, water conservancy, and banking video images, audio, data, Ethernet, phone, and other optical transceiver began a large number of applications.
Due to the digital optical transceiver with high transmission signal quality, no analog FM, phase, amplitude modulation optical transmitter and receiver with multi-channel signal interference during turn seriously, vulnerable to the effects of environmental noise, poor quality of transmission, the long-term stability of shortcomings, many large projects has been widely used digital optical transceiver.
System framework and working principle
The entire system is the core control module FPGA, audio sample codec module and separation module, video video amplifier modules, video A/D and D/A conversion modules, and string/string and convert module, optical fiber modem transceiver modules, power supplies, control module and 485 data transfer modules.
Figure 1 is a diagram of the system.
Figure 1 system architecture diagram
System working principle: optical transceiver system is divided into two parts: a transmitter and receiver.
In the transmitter from the monitor, or other video source of video signal first after launch onboard video noise removal filtering network signal, and then on the video signals for video and video magnification. Video separation module get video signal lines, field sync signal and the odd field signal, video clamp and other important video information. Next, to enlarge the video signals after A/D conversion, digital video signal into the system master core FPGA. At the same time, if the system detects the audio signals are present, the audio filter, audio, digital PCM sampling, and audio. After the PCM encoded audio signal, fed into the system master core FPGA. Reverse data transmission mainly 485 signal, the signal is fed to the FPGA. In this way, the system master core FPGA from different modules of video, audio, data, and other signal integration, time division multiplexing in various signals encode 8-bit parallel signal flow into and string conversion module. Signal flow through and string converted into high-speed LVDS signal fiber-optic transceiver modules to WDM way finished electrical/optical changes and light emission. At the receiving end of the optical transmitter and receiver, after the above process, complete the raw signal of recovery.System hardware
1 FPGA core controller
System core control part is in the heart of the entire system, in order to meet the needs for high-speed, real-time multi-channel data stream handle system core controller must have a high operating frequency and response capacity.
Secondly, the system time division multiplexing components, in order to signal synchronization, you need the system core controller embedded RAM and FIFO function blocks. In addition, at the same time as an embedded system, the processor must have low power requirements. Currently, FPGA processor has been around the industry control, consumer electronics, communications systems and other products on the market. In accordance with the low-cost, low power consumption, small size, versatile and more powerful data handling capabilities, Altera CycloneII series EP1C3144 company is a very good choice.2 video separation module
The video signal in addition to containing the image signals, including a line sync signal, the signal line hidden surface removal, field synchronization signals, signal and slot blanking pulse signal, the former balanced equilibrium after the pulse, pulse, therefore, to make the video signal acquisition, it is necessary to accurately grasp the logic between the various signals.
LM1881 is video signal synchronization separation and production to video signal processing provides great convenience. This circuit is designed as shown in Figure 2.
Figure 2 video separation circuit
LM1881 from 0.5 ~ 2V standard cathode-NTSC, PAL, SECAM system video signal in composite sync field sync, parity field recognition, signal, the signal is digital image acquisition required synchronization signals, with them, you can determine the collection point in which field, which row.
LM1881 also on non-standard video signal synchronization separation, through a fixed time delay generates default output as field synchronization output.3 A/D and D/A conversion module
Here's A/D conversion circuit is mainly used to enlarge the video filter, video signals after the digital transformation.
TV picture signal bandwidth calculation value is the actual extraction 5.5275MHz 7.37MHz. By Shannon's theorem, the ADC sampling frequency should be greater than 2 times the maximum frequency of the image, so the ADC using ADI's AD9280, operating frequency as 32MHz. The ADC has good differential nonlinearity, analog input beyond conversion range hints, built-in self stream-level responses and adjustable on-chip voltage reference, and other advantages.Here A/D conversion circuit design as shown in Figure 3.
Figure 3 A/D conversion circuit
Receiving A/d conversion circuit finishes after the main digital signal of analog video, restore the standard transformation of video signals.
Here the DAC selection to ADI's high-speed AD9708.AD9708 adopts + 3V or + 5V single supply, two-channel current output, the conversion rate as high as $ 125MHz, the establishment of time of not more than 35ns, conversion accuracy to 1/4 LSB.
At + 5V power supply, the power consumption for 175mW; + 3V power supply, its power consumption to 45mW.For special needs, AD9708 also compatible with 8-bit,
10-bit and 12-bit parallel data input. When AD9708 is set to 8-bit data type, as long as the pin 1 is set to maximum input valid data bits (MSB), pin 8 is set to minimum enter valid data bits (LSB). Pin 1 (DB13): maximum input valid data bits; pin 2 ~ 13 (DB12 ~ DB1): data input; pin 14 (DB0): minimum input is valid.Low-voltage differential signaling by ANSI/TIA/EIA-644-1995 defined for high-speed data transfer of the physical layer interface standard (LVDS).
It has a very high speed (rate can reach 1.4Gb/s), low power consumption and low radiation characteristics, which is implemented on the copper media Gigabit rate communication optimization scheme. By bus-low-voltage differential signaling LVDS is LVDS technology in multipoint communication areas, it requires greater driving current (10mA) and better impedance matching design.SN65LV1023 and SN65LV1224 is TI company launched in 10-bit bus low-voltage differential signaling of chipsets.
Which is to 10 SN65LV1023 bit parallel CMOS or TTL data converted to have embedded clock difference of high-speed serial data streams with absorber; while SN65LV1224 is receive the difference data streams and convert them to parallel data of SerDes, it also can rebuild parallel clock. Use of the device group in the data string is embedded clock, so you can effectively address the clock and data not strictly synchronization constraints on high-speed transmission bottlenecks. Here's the hardware circuit design shown in Figure 4.
Figure 4 and string conversion hardware schematics
System software design
System software is the core of the system control FPGA programming.
The entire program is based on the modular and structured software development ideas. The development tool is the Altera Corporation of FPGA QuartusII integrated development environment, development languages in today's more popular LSI Verilog development language.System software functionality for A/D control module, speech coding control module, and string conversion control module, string and convert the control module, D/A control module, voice decoder control module and reverse data transceiver control module.
1 A/D control module
A/D control module to FPGA core for the master to provide sampling clock AD9280; at the same time collecting AD9280A/D converted number.
FPGA system clock frequency is 32MHz, AD9280 sampling clock 16MHz, second to the system clock frequency is supplied to the AD9280.
At the same time, in the frequency of the output after the rising edge of the clock on the A/D conversion results for reading, the results are read into the FPGA to the next step in the application. The program follows.module AdControl(clk_in,reset,ad_data,clk_out,data_reg);
input clk_in,reset;
input [0:7]ad_data;
output clk_out;
output [0:7]data_reg;
reg [0:7]data_reg;
reg clk_out;
always@(posedgeclk_in)
begin
if(reset)
clk_out<=0;
else
clk_out<=~clk_out;
end
always@(posedgeclk_out)
begin
data_reg<=ad_data;
end
endmodule
Of these, the FPGA system clk_in input clock; after the crossover clk_out available to ADC sampling clock, reset to reset client reset Reset; ad_data is A/D conversion of digital content; data_reg used to store A/D converted number.
2 voice coding control module
Speech coding control module mainly completed PCM coded chip provides data encoded clock, data-enabled control, as well as encoded data reception.
Here is shown below.
module PcmControl(clk_in,reset,tdd,tdc,tde,pcm_data);
……
always@(posedgeclk_in)
begin
if(reset)
begintdc<=0; end
elsebegin
if(cnt0==7)
begin
tdc<=~tdc;
>cnt0<=0;
end
else
cnt0<=cnt0+1;
end
end
begin
if(cnt1==140)
begin
tde<=~tde;
cnt1<=0;
end
else
cnt1<=cnt1+1;
end
begin
pcm_data<=tdd;
end
endmodule
Where is FPGA system clock clk_in, reset the system reset signal.
Signal tdd is output PCM coded chip; signal pcm_data holds PCM encoded data; signal tdc is PCM clock signal; signal tde is PCM coding at the clock.System master core FPGA digital video, voice signal for TDM voice, video and mixed-signal sent with converters.
And string conversion module main realization on and string converter timing control, the control and data input control. Here's part of the program are as follows.moduleSnControl (clk_in,fpga_data,sn_clk,sn_data,sncontrol);
input clk_in;
input [0:9]fpga_data;
output [0:9]sn_data;
output sn_clk,sncontrol;
reg sn_clk,sncontrol;
reg [0:9]sn_data;
always@(posedgeclk_in)
begin
sn_clk<=~sn_clk;
end
always
begin
sncontrol<=1;
end
always@(posedgesn_clk)
begin
sn_data<=fpga_data;
end
endmodule
Where is FPGA system clock clk_in, signal sn_clk is and string converter conversion clock; signal fpga_data is FPGA on video, voice, TDM encoded data signal sn_data is and string converter input data; signal sncontrol is and the encoding of string converter enabled clock.
4 D/A control module
D/A control module used mainly to control AD9708, from string and converted data, FPGA place when decomposing multiplexing, and then move the video signal sent to the DAC AD9708 to support the conversion clock, the clock signal through and string converter recovery through emitting client-side system for transmitting clock.
Conclusion
This set of digital optical transceiver system, individual monitoring points and the control room of the signal transmission.
The control point of the camera back to the video signal, control room by 485 data interface cable to the camera for remote control. Distance between the two ends can also be used for voice communications. Have a certain value and meaning.
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