Embedded digital based S3C2510A DVR design (1)

Digital hard disk recorders, the English name is short for Digital Video Recorder, DVR, video monitoring system in important equipment, used in place of the early long time¨cdelay or tape recorder.

The current hard disk recorders on from the hardware architecture is mainly divided into gongkongshi DVR (or industrial DVR or PC-DVR), DVR, from the compression algorithm to score the wavelet compression, MJPEG, MPEG4, H.264, etc. Currently gongkongshi DVR and DVR market share accounted for by more or less the same, as the DVR's stability and easy maintenance, select DVR users will more and more, market prospect is very large. Application based on this background, this article proposes a DVR to design and implement programmes.

The overall scheme of the system

1 specification

This system the main technical indicators are as follows.

• Video input: 16 channel composite PAL/NTSC video input.

• Video output: composite video output 2-channel PAL/NTSC (BNC interface, 1.0VP-P, 75 Ω).

• Audio output: 16 channel audio input 20 ~ 100 m V 10 k Ω (RCA).

• Audio output: 2-channel audio output, 20 to 100mV, 1 k Ω (RCA).

● System resources: while multi-channel video, while playback, network operations at the same time.

● Image compression: enhanced H.264, video and audio signal compression generates a composite of H.264 stream, the stream playback of video and audio synchronized.

You can set a single video stream.

• Audio compression: G.729

2 design

According to the system requirements specification, this design 16-way embedded DVR system hardware part incorporates a schema master-slave dual CPU mode.

The main CPU use ARM9 processor, specific models for Samsung semiconductor S3C2510A, selection from the CPU, DSP processor specific models for United States Texas instruments (TI) multimedia processing chip TMS320DM648. Master-slave CPU over the PCI bus to communicate.

The entire system workflow design for: System power-up or reset the primary CPU S3C2510A from Flash loader, to complete the chip initialization and peripheral hardware configuration, after the start from CPU TMS320DM648 for image acquisition.

From the CPU via I2C port on the system's video decoding chip control, will be collected from camera analog video signals into digital video signals into DM648 video channel (VP port); synchronous acquisition of analog audio signal through the audio codec die/number after conversion, fed into the audio channel DM648 (McASP port). DM648 will receive digital video and digital audio signal compression data respectively, then the compressed video stream and compressed audio stream to sync composite, producing H.264 video composite stream, and then through the PCI bus to the main CPU, main CPU will receive from the PCI interface to the data storage format of the file to your local hard drive for future calls, synchronization will composite data spread for image preview chip to display. The entire DVR system framework diagram shown in Figure 1.

Figure 1 DVR system block diagram

System design

1 Introduction to S3C2510A ARM9 processor

S3C2510A is Samsung semiconductor production of 16/32-bit RISC microcontrollers, ARM9 processor series, are for Ethernet-based system for low-cost, high-performance micro-controller solutions.

2 introduction to digital signal processor TMS320DM648

TMS320DM648 is a TI company in 2007 launched a high-performance 32-bit fixed-point DSP, mainly for digital media application C6000 DSP series, belongs to.

DM648 retains the original kernel structure C64X, operating frequency by internal frequency multiplier settings, you can reach 720MHz, 800MHz or 900MHz, corresponding clock cycle to 1.39ns, 1.25ns or 1.11ns per second executable directive number 5760, 6400 and 7200MIPS.

In addition DM648 tablets with five dual-channel (2 channels A, B) digital video port (VP), can also handle multiple digital video streaming, on-chip serial with multi-channel audio interface, can simultaneously handle 10-channel stereo input/output audio signal.

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