I. preface
Because of work, design a single bi-directional double machine communication protocol.
Requirements for host through its with keyboard control of the host and from the machine's display, from the machine also can through the band's keyboard control host and displays from the machine, the host and from the machine plays the keyboard control function, display it exactly.In addition, from the machine can be separated from the host.
When machines from offline connect the host requires that the host from the function display immediately, that is, the keyboard information displayed double machine.2. Design Overview
1. the overall timing:
2. the host receives the data from the machine to send data in time series:
3. the host to send data from the machine receiving the data time series:
4. the symbol for instructions:
S: start-bit
A: response-
E: end bit
R: read ports
W: write port
Dx: data
5. slave synchronization principle:
The figure shows, the slave of reading and writing are mutually conflict, any time only allows one to write, but the two are in read mode.
Generally speaking, the data is transmitted by a frame, but from the timer interrupt is concerned, the data is the bitwise transmission because a timer interrupt only transfer a bit instead of the full frame data. In the data transfer is not started, from machine IO in edge interrupt receive status, the timer interrupt is turned off. The host will always be scheduled break state. When a host issue a start bit, if it exists from the machine, issued from the opportunity to respond to a low level; otherwise, it indicates that the communication fails after several clock cycle, the host will then initiate the next start-bit data transfer. In the communication process, any response bits are not set up, while declaring communication fails to end this communication.In summary, the data transfer starts, rely on the "external edge interrupt" synchronization, data transfer, rely on the "timer" synchronization.
6. Protocol of conservatism
(1) speed problems:
A single drop machine, CD player, etc. are charged as an example, as the processor's main task as signal processing, require communication takes less time, and the amount of data communications, this agreement is based on the design of the class.
Because every time you send a data only, it takes up very little MCU time.(2) reliability problems:
In this agreement, there are two response bits, an end bits, flags, such as the legitimacy of data provides a basis for testing.
In addition, because the slave simply transfer single drop machine, CD player, etc. of the "press" or "State" of the data, the data volume is not 8-bit, extra bits can be used to validate such as parity, Hamming, etc.(3) effect of detection
Adopted by two AT89C51-chip system consisting of the test, which work completely normal, and plug your host, you can always from the machine and disconnect the plug without affecting the master-slave machines work status and display.
The agreement was a well-known enterprise single-drop machine for mass production.1. the host source program
; Host program
KBUF0 EQU 24H; key temporary buffer
KBUF1 EQU 25H; key buffer
KCNT EQU 26H; keyboard repeat count
DLYD0 EQU 27H; delay variable
DLYD1 EQU 28H; delay variable
DLYD2 EQU 29H; delay variable
RSCNT EQU 2AH
RSI BIT 00H; transceiver start flag
RSF BIT 01H; transmit/receive flags
RSF0 BIT 02H; transceiver flag 0
RSF1 BIT 03H; transceiver signs 1
; SDF BIT 04H; data send logo
RDF BIT 05H; receive data labels
STATE EQU 2BH
SDATX EQU 22H
RDATX EQU 23H
CTPIO BIT 0B2H
TSIOBIT 0B3H
ORG 00H
AJMPMAIN
ORG 0BH
AJMPINT_T0
ORG 100H
MAIN:
MOV S
P,#50HMOV KBUF0,#00H
MOV KBUF1,#00H
MOV KCNT,#00H
MOV STATE,#00H
MOV SDATX,#00H
MOV RDATX,#00H
MOV RSCNT,#00H
MOV 20H,#00H
MOV P0,#00H
CLR RSF
MOV TH0,#00H
MOV TL0,#00H
MOV TMOD, # 02H; working mode for timing mode 2
MOV TCON, # 10H; allow timer 0 work
MOV IE,#82H
LOOPX:
CALL KEYREAD; reading keyboard
CALL DLY2MS; latency 2ms
JMP LOOPX
; Key function entry
FUNCTION:
MOV A,KBUF1
CJNEA,#07FH,FUN1;+1
;MOVA,STATE
;ADDA,#01H
MOV A,#01H
MOV STATE,A
CPL A
MOV P0,A
;SETB SDF
JMP LOOPX
FUN1:
CJNEA,#0F7H,FUN2;+2
;MOVA,STATE
;ADDA,#02H
MOV A,#02H
MOV STATE,A
CPL A
MOV P0,A
;SETB SDF
JMP LOOPX
FUN2:
CJNEA,#0BFH,FUN3;+4
;MOVA,STATE
;ADDA,#04H
MOV A,#03H
MOV STATE,A
CPL A
MOV P0,A
;SETB SDF
JMP LOOPX
FUN3:
CJNEA,#0FBH,FUN4;+8
;MOVA,STATE
;ADDA,#08H
MOV A,#04H
MOV STATE,A
CPL A
MOV P0,A
;SETB SDF
JMP LOOPX
FUN4:
CJNEA,#0DFH,FUN5;+16
;MOVA,STATE
;ADDA,#10H
MOV A,#05H
MOV STATE,A
CPL A
MOV P0,A
;SETB SDF
JMP LOOPX
FUN5:
CJNEA,#0FDH,FUN6;+32
MOV A,STATE
;ADDA,#20H
XRL A,#08H
MOV STATE,A
CPL A
MOV P0,A
;SETB SDF
JMP LOOPX
FUN6:
CJNEA,#0EFH,FUN7;+64
MOV A,STATE
ADD A,#40H
MOV STATE,A
CPL A
MOV P0,A
;SETB SDF
JMP
LOOPXFUN7:
CJNEA,#0FEH,FUN8;+128
MOV A,STATE
ADD A,#80H
MOV STATE,A
CPL A
MOV P0,A
;SETB SDF
JMP LOOPX
FUN8:
JMP LOOPX
;==================================================================
KEYREAD:
CLR P2.7
SETBP2.6
MOV A,P2
ANL A,#0FH
MOV KBUF0,A
SETBP2.7
CLR P2.6
MOV A,P2
ANL A,#0FH
SWAPA
ORL A,KBUF0
MOV KBUF0,A
CJNEA,KBUF1,KEYRD4
MOV A,KCNT
CJNEA,#03H,KEYRD1
RET
KEYRD1:
INC A
INC KCNT
CJNEA,#03H,KEYRD5
MOV A,KBUF1
CJNEA,#0FFH,KEYRD2
RET
KEYRD2:
POP A
POP A
;MOVP0,A
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