Based on the high-definition video compression ADV212 system design (1)

Along with the social information increases, people on multimedia video compression of increasingly demanding, "high compression, low bit-rate video compression of high definition" has been widely used in household appliances, medical equipment, military reconnaissance, satellite remote sensing, etc.

ADI's newest ADV212 is a real-time compression/decompression standard (SD) video signals and high-definition (HDTV) video signal device with reliability, flexible configuration, support for various video formats, etc., applied to various video formats of the data processing. This article describes the ADV212 HD video compression based system design, the system can support SMPTE274M (1080i) video live encoding.

1 principle of codec ADV212

As shown in Figure l for ADV212 features figure, mainly by pixel interface, wavelet transform engine, entropy coding/decoding, embedded RISC processor, storage system and internal and external DMA, etc.

Operation of the basic process is video or pixel data input through the ADV212 pixel interface, efficient sampling values the interlaced transmissions to Wavelet transform engine (Wavelet transformation engine, you can code block for up to 6 levels of Wavelet Decomposition). Enter the wavelet transform engine data is divided into tiles or frames, each of the tiles or frame 3 through 5/9/fixed-point arithmetic or 7 floating-point arithmetic filters into many of the band, and generates the corresponding Wavelet coefficients, then write internal registers. 3 entropy coding/decoder used Wavelet coefficients of coding blocks for a background modeling and arithmetic coding and compression process calculation best rate and distortion. Entropy encoding form of JPEG2000 standard data stream was deposited into code FIFO. Code FIFO buffer internal high speed bus mainly and low speed host interface. Stream data can be used to read and write access protocols (, ADDR) output from the host interface, or by DREQ/DACK agreement by external DMA controller coordination of external DMA engine output. Internal DMA engine complete storage as well as between the various modules and storage of high-bandwidth, high-performance transport. RISC processors with each program and data memory, interrupt controller, standard bus interface and timer counter the ROM and RAM.

2 Commission hardware design

Implementation of this programme as a high-definition video compression system, first of all from the system to implement the functionality and price considerations, using FPGA + ADV212.

Video decoder selection: video decoder selection ADV7402-type high-definition video decoder.

It takes 10-bit ADC, 12 analog inputs, support SDTV (480i, NTSC, PAL, SECAM), HDTV (1080i, 720p) and graphic RGB input (1 280xl 024 @ 60 Hz) and ADV212 seamless connection.

ADV212 number selection: 1 x 10-bit high-definition (HDTV) video signal, enter the data transfer rate of approximately 124 Ms/s, while the ADV212 pixel interface input rate limiting, irreversible mode to 65 MS/s, reversible mode 32 MS/s.

This requires the system to at least made up by 2 tablets ADV212, the system selects the 2 tablets ADV212 compression devices, YCbCr data taken in 4: 2: 2 format, complete the brightness (Y) and chroma (CbCr) data compression, the input data using the EAV/SAV encoding format. Figure 2 shows the system structure diagrams, the programme includes video capture decoding module, video image compression module JEPG200, compression, merge module, logic control modules and communication output module.

Select: selection of Altera FPGA company CycloneIII series EP3C55F484C8 devices, its I/O with 328 users, 55 856 available logical element, 312 embedded multipliers unit and 4 phase-locked loop, you can easily implement ADV212 initialization and compressed data capture and brightness of the compressed data and chroma compression data merge.

3 ADV212 device initialization process and parameter configuration

3.1 ADV212 initialization process

ADV212 initialization procedures according to the specific directive command to configure the internal direct registers and ADV212 indirect register to complete.

Figure 3 shows the initialization process, the ADV212 code to initialize the program from PLL registers, registers, BOOT MMODE registers and BUSMODE registers, direct registers Access, access directly register must be kept on the target system when the input pin, ADDR, and HDATA (write) State. When loading the firmware and configuration parameters, software reset, and then configure again and BUSMODE MMODE registers and use special registers. Next, to determine the correct firmware to be loaded on application ID. The correct firmware loading can be EIRQFLG register interrupt or voting procedures. When you determine the firmware connected load and EIRQFLG register is cleared to zero. Coding begins.

3.2 ADV212 parameter configuration

Clock configuration: 1080i high-definition video requires VCLK 74.25 MHz.

According to the datasheet, JCLK ADV212 must be at least 2VCLK, hence the maximum pulse frequency, it is recommended to 0.35J-CLK nearly 50 MHz, this is the maximum read and write pulse frequency.

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