Based on FPGA platform against DPA attacks circuit-level protection technology research (1)

0 introduction

In recent years, the FPGA (Field Programmable Gate Array, FPGA) due to its high performance, low price, high speed and easy programmatic features has been widely used.

But on FPGA for DPA (Differential Power Analysis, differential power analysis) attacks have become FPGA application information security one of the main threats, has received widespread attention.

DPA is SCA (Side Channel Attacks, bypass attack) technology, its attack thinking: circuit power consumption is based on the use of power and the relationship between the internal key, to a large amount of sampling that contains the internal key operation of power waveform data according to the conjecture of key partitioning, the divisions of the two parts with different power consumption characteristics.

Finally, the two parts of the power consumption data subtraction get power difference curve, if you guess correctly, difference curve appears obvious spikes.

Therefore, for DPA attacks the root cause is a logical representation of the circuit is not symmetrical.

This article will apply the structural characteristics of their own FPGA, combined with the current popular resistance to DPA attacks of circuit-protection technology, in-depth research and analysis in FPGA platform implementation for DPA attacks of circuit-protection technology.

1 FPGA circuit protection technology

1.1 FPGA underlying structure

FPGA simplify structures as shown in Figure 1.

FPGA internal main, design engineering most need concern part is a CLB (Configurable Logic Block, you can configure the logical block), IOB (Input/Output Block, input/output block), Block RAM (block RAM), DCM (Digital Clock Manager, digital clock Manager) and Multiplier (multiplier). CLB is FPGA with which the programmability of the main principals, a slice of Virtex-5 main unit includes 4 6 input look-up table, four triggers and several selector.

1.2-track circuit technology implementation

-Track circuit technology refers to both the input or output is represented by two lines.

Figure 2 shows that in the SDDL and gate, A signal from A and the common representation, and the output from the Z and Z. In this representation, a variable can have 4 different logical values (0, 0), (0, 1), (1, 0) and (1,1). SDDL is (0, 1) and (1, 0) are used to represent logic 0 and logic 1. This circuit internal logic 0 and logic 1 becomes symmetrical, which makes their own power. In addition, logic gates also introduces a prch pre charge signal. In prch are valid, the output is (O, 0), this value is the variable is a pre charge in the circuit of representation. Circuit of the work is divided into two States: operation status and charging status. The two State alternate replacement, which is loaded in prch a fixed cycle pulses. This circuit variable value changes is (0, O) to (O, 1) or (a, O), or (0, 1) or (1, 0) to (O, 0), every time you flip is only one signal line flip. Logical O and logical 1 reached the full balance.

1.3 pre charging technology implementation

General logic gate does not provide continuous conversion activities, logic gate input unchanged will cause the data independent of the door.

To solve this problem through increased pre charge circuit to provide transformation. When the clock is high, connecting pre-pre-charging circuit input a charging phase, connection point changes to logical O; when the clock is low, the circuit input calculation phase, the actual calculation is completed. In the FPGA on the use of pre charge logic is required in advance during the charging phase slice of output must be logical O, there are two ways to complete. In a Xilinx's slice, each LUT followed specialized multiplexer and memory modules can be configured to register, or latches. Here, consider using a multiplexer and memory modules for pre charge, each method has advantages and disadvantages:

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