Based on the DSP and USB data acquisition and processing system design

In the image data processing system, often need to conduct high-speed signal acquisition and processing.

For example, in the optical sensor technology for optical pulse scattering measurements, in the radar project on the measurement of electromagnetic pulse signals are needed for high-speed signal acquisition and operations carried out, and this type of high-speed signal measurements, often on data acquisition and processing system of strict requirements. This article design and implementation of DSP and USB data acquisition and processing system. The system circuit is simple, good reliability, with a certain degree of commonality and can carry multi-channel expansion.

　　

　　

1 principles

　　

Based on the DSP and USB data acquisition and processing system of the block diagram shown in Figure 1.

System power-on, DSP, FPGA separately by the respective FLASH loader, acquisition and processing system to start running. In A/D converter complete converted from FPGA to DSP send a break signal, 0 for DSP from A/D FIFO to read data in RAM and Wavelet denoising, when you are done working with the DSP send to USB controller, interrupt request signals will be processed after the USB controller of the data sent to the PC, the host application displays the data. Host applications can also be on the entire collection, processing and control system, the main set of three features: receiving and processing data, receiving and processing the data set before A/D sampling frequency and sampling points.

2 system hardware design

　　

System hardware design is mainly divided into three parts: DSP part, FPGA, USB.

2.1 DSP part design

This system uses a DSP chip for TI (Texas instruments) company TMS320VC33, it is a TI company launched the cost performance is extremely high in 32-bit floating-point digital signal processing chip, is currently the most widely used at home and abroad by one of the floating-point DSP.

TMS320VC33 has the following characteristics: Harvard architecture; line; dedicated hardware multiplier; special DSP instructions; fast instruction cycle.

In addition, TMS320VC33 also has powerful floating-point operations, operation speed can reach 150MFLOPS (million times per second a floating-point operation), processing capacity reached 75MIPS (million instructions per second cycle). Moreover, it also adopts 3.3V I/O processor core voltage and 1.8V less power voltage allows to 200mW.

　　

DSP part of circuit design primarily for TMS320VC33 perimeter circuit design.

TMS320VC33 STRB0 and PIN of the connected storage chip selected and enable pin, the realization of program/data memory expansion; pin received a high level, INT2 pin received a low level, power-on self loading after program; by TMS, TDI, TDO, TCK,, such as pin EMU1 EMU0, consisting of program downloads, to facilitate the DSP program debugging.

2.2 FPGA design

Because this system of logic is more complex, in order to effectively reduce the hardware volume, improve the reliability of the hardware system, where all the logic of the control circuits, various memory/register address decoding circuit with a large-scale field programmable logic gate array (FPGA) XC3090.

Logic control circuit including: command registers, sampling points/sampling frequency setting register, interrupt request signal generator, the results of the a/D write FIFO RAM control circuits, USB and A/D FIFO and FIFO status detection circuit.

2.3 USB design

TMS320VC33 and USB controller with bi-directional between AN2136SC FIFO Exchange data, handshake signals use PCs AN2136SC.

When the USB to receive buffer, the DSP read, write, when USB AN2136SC to send buffer, write, read AN2136SC DSP. PC (0) ~ (3) used for both read and write channel, direction programmable determine; PC (4) an application for TMS320VC33 AN2136SC; interruption to PC (5) is used to reset the USB receiver buffer AN2136SC; PC (6) for the USB receiver full marks, if the receiver is full then prohibit AN2136 further USB receiver buffer write; PC (7) for USB send buffer empty sign, if buffer is null then the ban AN2136SC further read on USB send buffer.

3 system software design

System software including five most: DSP program (for A/D sampling control, data processing, DSP and USB information exchange between), USB drivers, USB firmware (for the PC and the data exchange between the DSP and processing), the host application, the FPGA on address decoding programs and individual registers of realization of the program.

3.1 DSP program

DSP program first initializes the DSP (interrupt initialization, tablets, selected correspondence, initialize, set the system default sampling points/sampling frequency, etc.), and then wait for interrupt (interrupt 0 program is mainly used for A/D data is read and processed, and to host sends the processed data; interrupt 1 program is mainly used for the analysis of the host command, the command set for the host system of sampling points/sampling frequency, and sends the host required data).

Programs block diagram shown in Figure 2.

　　

　　

3.2 USB firmware procedures

/P>

Firmware programming code from USB chip integrated Enhanced 8051 microcontroller.

When EZ-USB device to a USB port, and host bus enumeration, first under the device ID to use the system program will download the firmware to the chip, and then to enumerate, the firmware as the user's function device. CYPRESS company provides firmware program framework, used to complete the control transfer work and most of the data transfer. The interface circuit of firmware is a firmware based on this framework developed and compiled using Keil C. USB receiver for DSP break program are as follows:

void　 ISR_IDT(void) interrupt INT0_VECT

{FASTXFR = 0x40;

Enabling rapid transmission mode

AUTOPTRL=LSB((WORD)&IN4BUF);

Will automatically point to the endpoint 4 bumpers

AUTOPTRH=MSB((WORD)&IN4BUF);

for(i=0;i<64;i++)

{AUTODATA=ACC};

Receive data

FASTXFR=0x0;

IN4BC=64;

Send data size

EZUSB_IRQ_CLEAR();

IN07IRQ=bmEP4;

Enable endpoint 4}

3.3 host application

In order to achieve a communication with the driver, the application first create an event and a thread, and then set the event handle passed to WDM, thread waits for WDM send event messages, receive event messages, read the driver data, display data.

In Windows, the application calls the Win32 API function has five: CreateFile (), ReadFile, WriteFile () (), DeviceIoControl () and CloseHandle ().

Application to open a WDM device driver, use CreateFile () function.

It's the first parameter is a symbolic link name. If you use DriverWorks creates a WDM driver, usually used to generate a class KUnitizedName equipment symbolic link name. The name followed by a number that is normally a 0. For example, if a symbolic link named "L" USBDevice, passed to CreateFile () is ".USBDevice0".

Once the application is a valid handle to a device, it will be able to call the Win32 function, which will result in a corresponding to this device object by the IRP, sent to the driver and complete the corresponding function.

The code is as follows:

HANDLE hDevice hDevice= CreateFile(“.USBDe-vice0”,GENERIC_READ|GENERIC_WRITE,FILE_SHARE_READ|FILE_SHARE_WRITE, NULL,OPEN_EXISTING,

FILE_ATTRIBUTE_NORMAL,NULL);

//Open a handle to the device

ReadFile(hDevice,buf,n,&nRead,NULL);

//Reads

4 test results

The system hardware and software debugging has been successful, Figure 3-CCD under occlusion at half the original signal waveform.

This system can also be collecting and processing the image signal (e.g. CCD signal).

　　

　　

This article presents an approach based on DSP, USB high-speed data acquisition and processing system, detailed look at the system's hardware and software design method.

The use of the verification, the system is very well implemented on CCD signal acquisition and processing. Use of a large-scale field programmable logic gate array, reduces PCB production space and greatly increase the reliability of the system; the use of DSP processors, improves data transfer speeds and processing speed, and thus ensures that the system of real-time; completed by USB host controller and PC communication, with hot-swappable, easy-to-use, high transfer rate; and the whole system constitutes a reasonable and implementation methods are simple, practical value.

Reference documents

1 official chapter, Liu kingsmark .Visual C ++ .NET class library encyclopedia. Beijing: electronic industry press, 2002

2 Su t, rush Lihua .DSP practical techniques-Xi'an: Xidian University Press, 2002

3 .EZ-USB Jiang Yan Yung 2100 series monolithic integrated circuits theory, programming and application. Beihang University Press, 2002

4 permanent Xiaodong.

CPLD/FPGA senior application developer's Guide-Beijing: Beijing electronic industry press, 2003