An anti-SEU memory circuit of FPGA design (1)

O introduction

As China's aerospace industry's rapid development, satellite applications more and more widely.

However, complex and ever-changing space environment, in which the existence of various cosmic rays and high-energy charged particles, they run in electronic devices will produce all kinds of radiation effects. Radiation effects on electronics impact cannot be ignored, because the radiation can make the device performance degradation, as well as parameters, thus affecting the satellite for the reliable operation to shorten the service life of the satellite. Radiation effects on electronics of many, the most important have total dose effect (TID) and single-particle effects (S-EE). SEE the impact of mainly consists of single-event upset (SEU), single particles latch (SEL) and single-particle burned (SEB) and three types, which are most common in the SEU. In a variety of radiation effects, memory on the most sensitive, SEU, storage of anti-radiation first thing to consider is the design resistance SEU.

In fact, different space environment and application requirements, storage of quantity and quality have different requirements.

For example: upload instructions and download the State of space-borne instruments requires data has a high reliability, this time on memory capacity you have no special requirements; whereas in certain uses of image data, the data reliability is the lower, in which case you will need a large memory capacity. Therefore, in the use of specific anti-SEU method, but also because of their different situations and make appropriate choices.

This article will use the extended Hamming code (Extended Hamming Code) and TMR (Triple Modular Redundancy, TMR) method of combining, and using both of error detection and correction of different features, to make the correction mode SRAM with adjustable resistance SEU design.

This enables storage of SEU design. And the flexibility to access memory use.

1 extended Hamming and TMR correction principles

1.1 extended Hamming error detection and correction principles

Extended Hamming code is a commonly used to detect two wrong at the same time to correct a wrong encoding method.

It is in the Hamming code on the basis of the codeword to join a $ for all code is validated by the parity bit, called extended Hamming code.

Extended Hamming code is linear block codes, information and supervision of the Association may be represented by a group of linear algebraic equations.

(N, k) linear block codes coding is to establish r (where r = n-k) generate redundant bits of pose of equations, the equations and the resulting equations into kxn generation matrix G. Coding, you can pass information bit vector (k-dimension) multiplied by the generate matrix G, resulting in code word vector (n-dimensional) shown in the following type:

Will-(1) represents the set of equations for the transposition of the transform, you can get-(2), usually known as H-monitoring matrix.

Decoding, through oversight matrix H and readout of the codeword vector C product results can determine whether the code word.

To read the C code word vector multiply by monitoring matrix H is a zero-vector, it means that no error occurred; otherwise, the indicated code word after the store has been the impact of single event effects, an error occurs. Usually will oversee the matrix and readout of the codeword product of the vector C as S, known as validating child. When the code word in a bit error occurs, you will get unique S vector that is the vector only and code word error location, and has nothing to do with the code word C. You can navigate through S vector error location, and the error correction data.

As a linear block codes, extended Hamming code of length coding, for 2r information bit length 2r-1-r bit, namely (2r, 2r-l-r) extended Hamming code.

This design uses a 16-bit RAM memory, so the corresponding use (22, 16) extended Hamming code.

1.2 TMR correction principles

TMR is a common hardware redundant technology.

Its principle is the same set of hardware unit at the same time, the probability of error than in a single hardware unit on the probability of errors. Its basic approach is to add the required fault-tolerant hardware unit is increased to three times or more, and each cell of the output is connected to a voting machine, by voting machine select all hardware unit as a whole, the vast majority of the output value of output values. Figure 1 shows the TMR system map.

Figure 1, A1, A2, A3 three modules simultaneously perform the same operation, and its output to the voting machine, and then by the voting machine received a three-way comparison data.

If three modules at the same time gives the three identical output, all the way to output any voting as the correct output. If either the module error, its output is different from the other two modules, the voting machine is still output the correct results. If there are two modules at the same time, and into the same State, voting machine will mistakenly believe that this is the correct results and output, but this situation appears even though it is possible, but the probability is very small. Of course, if these two modules at the same time an error, but the faulted state is different from the voting machine at this point will not be able to make a choice, but you can generate interrupts.

2 memory configuration scenarios

Through extended Hamming code on the face and TMR two correction way of introduction, you can find it both have advantages for different environmental conditions and application requirements.

However, both scenarios for memory configuration requirements are different, so the entire circuit design, it is first necessary to make the following configuration on the memory.

This design uses a 3 piece 16bit of SRAM.

And using (22, 16) Hamming and TMR two correction method. For (22, 16), the General (16 + 8) bit of memory, but TMR, you keep using 16-bitStorage device. To support these two methods, you must first provide storage design a special type of memory allocation. This design uses as shown in Figure 2 configuration of memory.

For Figure 2 memory configuration scenarios, when the system work in TMR mode, all the films selected signal are the same signal, this constitutes a TMR need three 16-bit memory space; when the system work in Hamming code mode, they are al, ah, bh, a group, bl, ch, cl for another group, and were the same pieces selected signal, thus constitute two separate (16 + 8) bit memory space.

This design uses a 3 piece of SRAM 128 K×16bit, if you set each SRAM low 4K×16bit space work in TMR mode, you can see from the illustration, the SRAM chipset also has two 124 K× (16 + 8) bit of space to work on the extended Hamming code mode.

3 circuit design

Based on the above memory configuration options, this article is designed as shown in Figure 3-SEU memory circuit.

The circuit consists of four modules.

3.1 TMR module

In TMR work mode to complete the data write and read operations in a judgment of redundancy.

If you read the process found a piece of data in the RAM and the other three are different, on the film to the correct data in RAM write back; if you find three pieces of data in RAM are not the same, a break signal.

3.2 extended Hamming code module

In the extended Hamming code work mode, when writing data, encode; when reading data, then the corresponding decoding, and determine whether the data is in an error.

If a mistake is the correct value automatically write-back, if two of the above error, you generate interrupt signal.

3.3 mode select module

In the module's internal settings have a 32-bit mode configuration registers.

By mode configuration registers of low 18 advance purchase, you can set the error detection and correction circuit mode, you set the RAM memory configuration. According to the different application requirements for CPU, mode control module can enable error detection and correction circuit in extended Hamming code style and TMR way between flexible switching.

3.4 control logic module

The circuit module according to the circuit of the correction mode to control the read and write signal, and memory chip selected signal in order to correctly access the RAM contents.

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