Actel FPGA based nRF24L01 and intelligent detection system design (1)

Abstract: A wireless data transmission based on nRF24L01 chip and Fusion StartKit development board intelligent detection system. .By opening the ACK PAYLOAD nRF24L01 function realization system and PC-board two-way communication between, the use of Actel Corporation bus 8051S with APB3 in Fusion StartKit soft core system on chip development board built using MFC write interactive Windows environment .interface, realized with real-time data transmission, automatic obstacle avoidance, remote control functions such as intelligent detection system. .<P> Present some of the poor or dangerous environment where human exposure to site still can not detect, such as the dangerous situation in the mine tunnels, caves and other rugged terrain, it is difficult to obtain on-site parameters. .In this case, only the help of intelligent detection devices. .Intelligent Vehicle Control for easy operation and flexible, compared to other tools more easily qualified for carrier detection task, therefore become the preferred tool for a variety of detection equipment. .</ P> <P> intelligent detection system designed in this paper to the car as the carrier, the field parameters are measured in real time through the wireless module returns nRF24L01 PC, with fast and flexible features; in the actual work can be turned around and back .automatically avoid obstacles; also facilitate control of the car can be built through the MFC interactive interface using the mouse and keyboard on the remote control car. .</ P> <P> 1, System Architecture Design </ P> <P> Actel FPGA-based implementation of the system, using two Fusi. .nStartkit development board, a control panel as the car, the other as a transit board. .Vehicle control board is responsible for collecting temperature, humidity, onboard voltage, current road conditions and human testing, and other site information, driving the car running, while the information through the wireless sending and receiving site host computer control commands. .Interim board responsible for the received radio signal transmitted through the serial port to the PC, while PC-control instructions returned by the serial module is sent to the vehicle using a wireless control panel. .PC, interactive interface written using MFC to display information about the car where the environment, while providing the mouse, keyboard and other sound manipulation tools. .System structure shown in Figure 1. .</ P> <P> </ P> <P> Figure 1 System block diagram </ P> <P> 2, system hardware design </ P> <P> 2,1 wireless data transmission chip nRF24L01 </ P> .<P> 2.1.1 Introduction chip H </ P> <P> nRF24L01 NorDic Norway's integrated single-chip 2.4 GHz transceiver chip, as many as 125 channels to choose from, support 1 Mb / s and 2 .Mb / s transfer rate. .The chip SPI interface to read and write data and parameters configured to register mapping of the various registers to manage, but also has automatic retransmission, dynamic and effective message length (DPL), response signal carrying useful information (ACK PAYLOAD) and other advanced features. .</ P> <P> 2.1.2 Function </ P> <P> dynamic and effective message length (DPL) refers to the sending end of the nRF24L01 chip data area by writing with an effective length of the data to determine the current size of the data frame, and .receiver through the received data frame control field information rather than length of the data register defined in the extraction of valid data. .This feature greatly improves the utilization of wireless channel, while reducing redundant data transmission, reducing the data retention time in the air, and the data is the probability of contamination. .The CRC checksum with nRF24L0l automatic repeat function, effectively reducing the error rate of data while ensuring timeliness of data transmission. .</ P> <P> response signal carrying useful information (ACK PAYLOAD) nRF24L01 chip mean automatic retransmission and DPL open on the basis of two-way communications. .Figure 2 shows a pair of portable wireless module response time between the effective information data transfer process. .The main transmit module (PTX) finished the first one to send data, automatically set to receive mode, waiting for the main receiver module (PRX) send a response signal or response signal carrying valid data. .The main receiver module receives the main transmission module sends the data frame after the first one, if additional time is necessary valid data, then sending the ACK signal to send valid data. .The main transmit module receives ACK signal to continue receiving a valid signal, until no residual air and then start sending the wireless signal frame signal 2. .</ P> <P> can use the ACK PAYLOAD PC-vehicle system and bidirectional communication, the function solves the state led to manually switch the wireless transceiver wait mutual problems, while only need to control the on-board control panel .response time with valid information, you can reduce unnecessary communication process, greatly improving the system stability. .</ P> <P> </ P> <P> Figure 2 carry the 1 ACK PAYLOAD data transmission diagram </ P> <P> 2.1.3 achieve functional configuration </ P> <P> to achieve nRF24L01 .The ACK PAYLOAD functions need to go through the following steps: First, the basic configuration of wireless modules, including the sending and receiving mode selection (CONFIG), open the automatic repeat function (EN_AA), receives the address enable (EN_ADDR), when you ask, do not set the retransmission .zero (SET-UP RETR), etc.; and then open the DPL and the ACK PAYLOAD same function, to achieve these two functions, the first step must be completed after the ACTIVATE command with the nRF24L01 with 0x73 vaginal opening hidden by default the data of the two registers FEATURE .and DYNPD. .By setting these two registers can be achieved two-way data communication. .But we know that after the receiver open the DPL command to use R_RX PL WID read the current valid data length of data frame, while using W ACK PAY-LOAD command ACK PAYLOAD write FIFO. .</ P> <P> 2.2 Core 80515 architecture </ P> <P> Core 8051S is based on Actel has introduced nuclear 8051lP APB3 bus, compatible with all 8051 instructions, but also have 51 single-chip does not have many unique features: .</ P> <P> (1) with configurable JTAG debugging interfaces can be used to Flash_Pro Downloader as its debugging tools; optimize the speed of instruction execution, the internal set lines, enabling a single clock cycle instruction execution, and is a common .SCM 51 to 12 times. .</ P> <P> (2) using APB3 peripheral bus memory map structure and the SER management of peripheral registers, the external expansion of the 64 KB of data space as APB3 maximum 4 KB memory mapped peripheral register addresses, each .a APB3 peripherals occupy 256 B of the address, so it can add up to 16 peripherals. .</ P> <P> (3) using the graphical user interface CoreConsole software to add Core8051S the way, and other peripherals, is intuitive and convenient. .</ P> <P> [1] [2].