1-wire system TM card equivalent replacement of SCM

1 Introduction to TM card

TM (Touch Memory) card is a United States patent products of Dallas company.

It uses a single protocol communication, instant touch to complete the data read and write both non-contact IC cards, easy operation, and a contact-type IC card lianjiaxing, is the current price of the best one IC card. Its appearance is similar to a button (button) battery that can be embedded in the card, key ring, and other objects.

TM card through a multifunctional data line, address line, control and power cables with 1 thread for a single communication.

When a host is powered by the TM 500 k Ω impedance 50 Ω and switching between hosts, in response to a signal are pulled low duration (long or short) to represent digital logic (length 1, short to 0). Due to impedance switch increases to 10 000: 1, therefore, the contact points of contact resistance will not affect the digital signal of identification.

2 1wire communication protocol

Single bus is only 1 data cable, data exchange in the system, the control is represented by this thread.

Device (master or slave) through a drain or Tri-State ports to the cable, which allows devices to send data to free the bus, while other devices to use the bus. Single bus typically requires an external one about 4.7 k Ω of pull-up resistor, when the bus is idle, and its status as a high level. Master and slave communication can be done through three steps: initialize 1wire devices; identify 1wire devices; the exchange of data. Because they are a slave, only the host calls from the machine, from the machine to answer, so the host access 1wire devices must strictly follow the single bus command sequence that initialize, ROM command, function command. If a serial confusion, 1wire device will not respond to the host (search for ROM command, alarm search command).

SMC1990A1 is factory calibrated laser to a 64-bit ROM ID code, including the 48-digit serial number, 1 x 8-bit CRC encoding and one 8-bit product serial number.

Data follow the single bus protocol transport, for reads and writes of the power provided by the cable itself, without the need for external power supply.

3 SMC1990A1 equivalent replacement

Single bus technologies save I/O port line resources, simple hardware expenditure line, low cost, easy-bus expansion and maintenance, etc.

In the distributed control system has a wide range of applications. In a real application, you may receive TM card lost and damaged, if such a situation occur, often under a new TM card to set more than one collection point. If the collection point settings a lot, will waste a lot of manpower. At this point, use SCM to replace missing or damaged TM card becomes necessary.

3.1 system hardware

The system adopts AT89C51 as controller, and 24 MHz crystal oscillator.

In order to be able to adapt to the standard single-bus communication protocol, crystal oscillator frequency should be as high. Taking into account all single-bus communication protocol of the transmission is initiated by the host, so in order to respond to the host as soon as possible, using the interrupt handling. Select the INT0 AT89C51 (i.e. P3.2) as cathode equivalent replacement SMC1990A1. Figure 1 is equivalent to replace TM.

　　

　　

Figure 1 TM card equivalent replacement

3.2 system software design

For an equivalent replacement SMC1990A1, mainly on time series analysis.

For SMC1990A1 child device, the main programming is for hosts, transmission is initiated by the host. Now replaced by SCM simulation SMC1990A1 child devices (now called "machine").

　　

　　

Figure 2 initialization sequence

First, the initialization sequence, as shown in Figure 2.

Host first sends a reset pulse, which lasted tRETL (minimum 480 μ s low level signal), and then release the bus and entry into the receiving State. From the machine to detect the bus after the rising edge, waiting time, tPDH from machine pulled down bus exists pulse, which lasted tPDL (low level, continuous 60 ~ 240 μ s), and then release the bus. Free bus pass la high bus.

Corresponds to the time series from the machine, the initialization of the interrupt service program flow shown in Figure 3.

　　

　　

Figure 3 initialization timing of the interrupt service program flow

The following is the host write 0 and write 1 time series.

After the initialization sequence, when host bus pull from high to low level, resulting in write-time gap. Start within 15 μ s should be required to write a bit rushed to the bus, after the start from machines at 15-60 μ s sampling on the bus. In the case of a low level, the write bit is 0, as shown in Figure 4; If a higher level, writes the bit is 1, as shown in Figure 5. Continuous write many clearance between tREC should be greater than 1 μ s.

　　

　　

Figure 4 host write 0 time series

　　

　　

Figure 5 host write 1 sequential

Corresponds to the from the machine, is waiting for the host computer command.

From machine waiting for host command interrupt service program flow shown in Figure 6.

　　

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Figure 6 commands from the computer to wait for the host of the interrupt service program flow

And finally the host reading data time series, as shown in Figure 7.

Host bus in the start time from a high level, to a low level, the bus simply maintain a low level 1 ~ 7 μ s. After release the bus at all times in tLOWR, generally in tRDV time sampling bus (15 μ s Office), the reading gap in tLOWR and valid between tRDV. From the machine must be in the moment former la tRDV higher or lower bus, host in tRDV time sampling, and in 60 ~ 120 μ s released bus.

　　

　　

Figure 7 host read data time series

On the slave, then to send the 64-bit ID processing.

Procedures for dealing with difficulty from the machine must be 15 μ s before la high or lower the bus for the host in 15 μ s Department sample bus. Procedures by determining bit address 00H State to enable this function. By determining bit address 01H State to determine the send-send-0 or 1. Sent from the machine to a 64-bit ID handling the interrupt service program flow shown in Figure 8.

　　

　　

Figure 8 64 bit from a machine send ID handling the interrupt service program flow

In the full realization of a ROM functions, from the machine first waiting for the host sends a reset pulse to be detected after Figure 9 implementing ROM function processes send presence pulse response.

Subsequently, from machine start receiving host sends ROM command, and save it to determine the next action. Finally, sent from the machine TM's a 64-bit ID code, complete a ROM command execution. Realization of ROM function in process as shown in Figure 9.

Microcontroller assembler are as follows:

ORG0000H

AJMPInit//skip to Init section

ORG0003H

AJMPJudge//jump to the interrupt service program

Init://initialize

MOVDPTR, # ID//ID table address

MOVR5,#001H

MOVR7,#000H

CLR00H

SETB01H

SETBP3.2

LCALLDelay10s

CLRP3.2//La low bus to wake the host

LCALLDelay100us

SETBP3.2

SETBEA

SETBIT0

SETBEX0

MAIN: AJMPMAIN//main loop

Judge: CLREX0//determine the implementation of the action, off break

JNB00H, SecondJ//skip to the second judgment

ID_IN: JB01H, SEND1//send from machine TM card 64-bit ID code

CLRP3.2//send bit 0

SEND1: SETBP3.2//send bit 1

LCALLDelay30us

MOVA, R5//R5 cycle move left

RLA

MOVR5,A

MOVA,#00H

MOVCA,@A+DPTR

ANLA,R5

CLR01H//set the 01H status

JZRelease1

SETB01H

Release1:SETBP3.2

MOVA,R5

ANLA, # 080H//determine whether the sent bytes

JZINTEND

INCDPTR

AJMPINTEND//jump to end interrupt

SecondJ: MOVA, R7//second judgment

JZWaitReply//skip to determine whether the command executed response receive end

ANLA,#008H

JZWaitOrder//skip to perform receiving commands

SETB00H

WaitOrder: LCALLDelay15us//receive command

NOP

NOP

MOVA, P3//sampling P3.2

ANLA,#004H

JZSAVE_R6

MOVA,#001H

SAVE_R6:

ORLA, R6//Save command to R6

RRA

MOVR6,A

RLOOP1:

MOVA, P3//determine host sends status, return

ANLA,#004H

JZRLOOP1

AJMPINTEND//jump to end interrupt

Waitreply://do answer

P>

RLOOP: MOVA, P3//determine the host in the reset signal

ANLA,#004H

JZRLOOP

LCALLDelay30us

CLRP3.2//from the machine, low level of response

LCALLDelay150us

SETBP3.2//release the bus

NOP

NOP

NOP

NOP

INTEND:

INCR7

CLRIE0

SETBEX0//opening break

RETI//interrupt returns

ID: DB001H//ID table

DB0C3H

DB04DH

DB057H

DB033H

DB022H

DB000H

DB0D2H

This code in the practical application is very good, to be able to achieve a stable alternative SMC1990A1 TM card ROM features that greatly facilitates the permissions managers for loss or damage of TM permissions management.

Reference documents

[1] SMC1990A1 Datasheet.

Version 0.1, June, 2004.

[2] Dr. Ying, Li guanghui. Single bus (1Wire Bus) technology and its application [J]. Foreign electronic components, 2003 (8): 47.

[3] Ding Yong, Li Hua-Hsi

TM card intelligent electronic locks and door control system [J]. Journal of Chongqing technology and business University, 2004, 21 (5): 488 490.

[4] Xu min, Zhuge Jin Jung, Sung and benevolence. 1Wire technology based digital temperature gauge [J]. Mechanical and electrical engineering, 2007, 24 (4): 26-29.

[5] Yang Wei fang, wild, Edward city, et al. DS1991 information button key crack and equivalent replacement [J]. Electronic technology, 2006 (12): 61-63.