Multiple-channel high-accuracy data acquisition circuit design

In the field of signal processing, application of DSP technology more and more widely, the DSP-based signal acquisition and processing platforms emerge.

Common DSP signal acquisition and processing platforms use bus for data acquisition, multiple devices on the bus data transfer often conflict with each other. ADI's Tiger SHARCl01-DSP (TSl01) only bus and chain junctions can communicate with peripherals, based on the purpose of alleviating bus conflicts, I designed a to field-programmable gate array (FPGA) as a data interface buffer, avoid the bus, the junction of chain TSl01 will be more of A/D converter collected data transfer to TSl01. By FPGA complete more multi-channel A/D converter collection data buffer sorting and meet TSl01 chain crossing transport protocol data stream sent to TSl01 chain junction. The design implements a chain junctions and other non-chain blocks external device communication. Reduces TSlOl bus data transfer rate, reduce bus competition problems.

2 ADS8361-type A/D converter

ADS8361 is a TI company production of dual-channel, four-channel, analog differential inputs, 16-bit serial synchronous sampling A/D converter.

4 analog differential inputs into 2 groups and each group member has 1 A/D conversion module, can be sampled; on each input can achieve 500 ks/s sampling rate, i.e. 2 μ s completes 1 A/D sampling. Sampling data output from the serial interface

, This is a synchronous serial interface DSP is very useful, DSP bus can hook a variety of other devices, high-speed continuous sampling process, the DSP serial and bus can work independently and do not affect each other.

ADS8361 in sampling frequency rate of 50 kHz, 80 dB suppression of common-mode, this strength is important in a noisy environment.

ADS8361 need analog voltage and digital voltage supply, taking into account the external circuit of match, select the analog part 5 V power supply, digital part and DSP I/O voltage, select 3.3 V power supply. Work can use internal 2.5 V reference voltage, can also be provided by the external reference voltage. Differential analog input signal voltage range ± 2.5V. ADS8361 adopts SSOP-24 package. CS PIN is ADS8361 slices; Ml, M0, AO PIN is used to select the sample channel and data channel; RD pin pins, for reads data CONVST pins is A/D conversion pulse, in use should be connected to the RD and CON-VST pin; CLOCK pins for input sampling clock (and later connected to the FPGA output ADCLK); 2-channel data output pin SERIAL DATA respectively A and B, each time the SERIALDATA transformation output 16 bit data. ADS8361 working clock Max 10MHz, high level and low level at least the 40 ns.

3 TSl01 chain junctions and transmission mode

TSl01 is a high-performance 128-bit floating point digital signal processor, the computing capacity is strong (18 billion times per second), and the external bus throughput capacity relatively insufficient (if external frequency of 100 MHz, external bus transfer rate of 800 MB/s), when peripherals during periods of high i/o bottlenecks are easily formed.

However it has four high-speed chain junctions each chain transfer speed limit at junctions to 250 MB/s for TSl01 point-to-point high-speed transmission between, and with the same protocol of peripheral communication, greatly easing the pressure on the bus.

Each chain TSl01 intersection by the transmitter and receiver of two parts, each part has a 128 bit-shift registers and 128 bit buffer register, its structure, as shown in Figure l.

Each chain junctions are 8 bit data and LxCLKIN, LxCLKOUT and LxDIR (x-chain junction ordinal 0-3) and three control pins, support for Tablet TSl01 processor bi-directional data between point-to-point transmission, it can also be used with an external device for data transfer. Which LxDIR used to indicate the data flow to the junction with the chain. LxCLKIN and LxCLKOUT to chain junction clock/confirmation handshake signals. When sending data, a clock signal, LxCLKOUT LxCLKIN to confirm signal; receive data, LxCLKIN LxCLKOUT for clock signal, a signal. Send data, the first 4 characters of data transmitted into the link send buffer register LBUFTx, then copy it to the shift register (if the shift register is empty, this can be written to the new LBUFTx data), and then send in a byte (send low byte first), each byte in the link clock rising and falling edge is driven and latches. The receiver of the shift register is empty, the system will start receiving the sender transmitted data and place it into the shift register, at the same time driving LxCLKOUT low-level. When the whole 4 words after receiving, if the receiving buffer register LBUFRx is empty, the 4-character data copied from the shift register, and in data LBUFRx is driven by its Lx-CLKOUT after copying to high level, to tell the sender receive buffer register is empty, ready to receive new data. Sender Lx-CLKIN detected as high level immediately after the next transmission.

　　

　　

Common start link for data transmission for two kinds of methods: using the IRQ interrupt startup TSl01 and start using the link.

Link to DMA, DMA is TSl01 kernel without intervention, the background through the chain of high speed data transfer junction. From external devices to transfer data at the chain, you are actually outside the chain junctionDepartment equipment sent data is automatically saved to TSlOl internal and external storage, you can also forward through other chain junctions. Junction on the chain and its DMA registers for the correct settings you can set the TCB block. DMA startup once link buffer is not full, it will request data to the external device. At this point, if DMA can use internal or external data bus, then the system will be able to move data from chain junctions to storage.

4 data acquisition hardware design

TSIOI is strong but the operation and external connection resources relatively few a DSP, in multiple TSl01 cascade system, if you use bus for data acquisition, A/D converters usually take a long time consuming bus, often between accounts problem, causing the signal acquisition and processing occur bus bottlenecks, use data acquisition at the chain can be largely free bus resources.

This application requires 10-channel analog signal at 500 kHz sampling rate, transmission of data to lOx0.5 MBx2 = 10 MB/s < 250 MB/s.

Conducted by FPGA TSl01 data acquisition, its chain junctions as data input.

Their connection structure as shown in Figure 2, the chain junction LxCLKIN direct and FPGA connections, by FPGA driven, in FPGA to chain crossing data is sent as a chain junction clock input. LxDIR and LxCLKOUT can vacant, chain Junction 8 data lines received on the FPGA.

Each design is A/D converter of the M1, NO, A0 PIN to ground, only to have each A/D converter, 2 analog differential inputs-AO and B0 channel, 2 channels can be in 2 μ s finish 1st within sampling.

This design with five ADS8361 level even for the expansion of the analog input channels, and achievement of 10 analog input channels, each ADS8361 of RD and CONVST connection is controlled by the FPGA, five ADS8361 at A/D conversions, the converted in FPGA within the complete string and converted to the converted parallel data first lock exists FPGA internal, and then press the channel first low byte after high-byte order are delivered to the chain TSl01 junction.

5 data acquisition software design

Software components including TSl01 software design and FPGA software design, software design using FPGA VHDL.

Its structure as shown in Figure 3.

FPGA's main action is to five ADS8361 10 road serial acquisition data into 20 8 bit data, data latches, and generate link clock, will latch data sent to TSl01 chain junction.

You need to implement the timing shown in Figure 4, where the CLOCK is TSlOl external clock, ADCLK is working clock ADS8361 is 5 crossover CLDCK, duty ratio is 60 percent, CONVST connected with RD, LINKCLK is link clock, LINKDATA is link data.

When using the link in the link clock TSl01 rising and falling edge is latch data, 20 8 bit data need lO link pulse and chain junctions each time you need at least 128 bit data transmitted, i.e. at least eight pulse, and send the data needed for pulse number must be a multiple of 8.

So the design of each time through the link sent data pulse number 16, top 10 transport A/D converter collected data, subsequent six pulse sent 0x55. The data sent to the link is to A/d converter last result of the conversion. TSl01 can set chain junction work clock kernel clock 2, 3, 4, 8, crossover, design TSl01 external clock CLOCK is 50MHz, kernel clock is a CLOCK frequency of 5 x 250 MHz, chain junction when receiving data link FPGA to TSIOI is 25 MHz clock LINKCLK TSl01 chain junction operating clock clock should be as close as possible to the link, so setting LINKCLK TSl01 chain junction work clock kernel clock 8 MHz frequency or 31.25.

System uses the link method receives data sent to FPGA, link interrupt mode data receiving program are as follows:

6 A/D converter circuit design and use

Design of high-precision A/D converter of the key is to ensure the effective number of bits, ADS8361 input dynamic range: ± 2.5 V, each quantitative units corresponding 0.076 mV, so you should try to reduce noise and interference.

Noise and interference sources there are mainly two kinds: one is the A/D converter's own noise such as quantization noise, etc., and the other is around circuit noise interference. The former is A/D converter built, whose size is far more than the former, particularly power, analog/circuit interference between digital circuits. ADS8361 differential input mode significantly reduces common mode interference. The main consideration in the design of the circuit to reduce other noise and interference.

Power supply design is the key to suppressing noise, this article describes design available in a wide range of voltage (analog 5 V,-V and 5 V digital 3.3, 1.2V, etc.) and is a hybrid of analog and digital signals for Board-level design, select the appropriate power supply circuit, reasonably be power layer and formation of cutting is very important.

Switching power supply with small size, high efficiency, output stability, etc., at the same time can be a good solution to the power-up sequence TSlOl, ripple. Switching frequency higher output voltage ripple, circuit chosen inductors in 10 μ H ~ 200Μ H suitable, circuits can use ESR small, large capacitor capacitance values constitute a decoupling circuit, at the same time the Board placed multiple filter capacitor.

Reduce the digital signal interference also can effectively improve A/D converter accuracy, cloth plate and wiring to make ADS8361 analog differential signal input range as far away as possible from a digital signal, FPGA design to avoid multiple signal level at the flip for A/D converters provide good working clock, use the tandem Terminal method, 1 small resistor in series can be very good timing jitter reduction, clock signal into A/D converter of the wiring as short as possible, but not too close from the digital signal, and not near the simulation area, otherwise it will increase the noise of analog area.

Also note single point total and the total of points threaded 1 beads. Design uses a multilayer PCB layout, in the light circumstances can output voltage ripple to 4mV.

7. closing remarks

I design a junction by TSl01 chain for many A/D converter for multiple-channel high-accuracy data acquisition methods, DSP signal acquisition and processing system can not take the bus, enabling parallel data transfer and processing, there are more real-time, at the same time that discuss how to improve the precision A/D converter.

The design has been applied to a variety of parallel and serial A/D conversion circuit with versatility.