Based on microcomputer intelligent elevator speech system design

Summary: this article has designed a chip-based intelligent elevator speech system, for the entire system of circuit, MCU, CPLD and decoder interface hardware such as a detailed exposition of the principle.

Software parts for elevator speech services requirements, through the elevator system special signal logic, to complete the elevator speech services in intelligent control and successfully implements the elevator speech services of intelligence and automation.

Introduction

Voice system on elevator is an indispensable part, such as a floor sound off, direction prompts, alerts, notices, fire intercom even advertising.

At present, the vast majority of elevator use speech chip for voice storage and playback, while the voice chip system has some drawbacks, such as the peripheral circuit complexity, the sound quality is poor, the cost is high, the capacity is limited and voice change inconvenience, etc. For this reason, this article is a microcontroller-based intelligent elevator speech system.

System overview

Elevator control system's basic functionality is based on the user's information, show floor press to go to floor numbers, voice reaches the floor.

System block diagram shown in Figure 1.

　　

　　

Figure 1 elevator speech system architecture diagram

Hardware design

According to the FLASH read/write rules and MP3 decoding agreement, the prior set of logical rules CPLD.

Controller in accordance with the input of information, to issue control CPLD and transfer data command. CPLD according to the received order in accordance with the rules of logic and to read and write FLASH MP3 set internal control register and transfer audio data. MP3 output analog signal can be directly promote headphone pronunciation, but if you need to promote the speaker, you also need an external power amplifier.

System micro controller adopts STC89C58RD + C, it is a new generation of 51 enhanced high-performance microcontroller, with encryption and strong anti-interference, Super, ultra-low power consumption, in-system programmable, can supply internal integration MAX810 special reset circuit and so on.

STC89C58RD + C with 32 k FLASH and EEPROM 16K of, and concern is its inclusion of 1280 Byte internal SRAM memory space, in the audio data processing and display data processing needs of larger data buffers, select it with the bulk of the MCU internal storage, the competent system control requirements.

This article uses CPLD responsible for logic control and data transfer.

CPLD circuits using XC9572-VQ64, it has a 72-unit, 1600 free gate circuits, I/O port, 52 with low-power, online 2.5V programming.

MP3 decoding chip VS1011E works and circuit design

VS1011E audio decoder chip for VS10XX series of third-generation product, its interior contains a high-performance, low-power DSP core, a 5.5KB chip RAM available for users to store code and data to a serial SPI bus interface, a two-channel sampling frequency adjustable 16-bit DAC.

Work at 12.288MHz ~ 14MHz or 24.576MHz ~ 28MHz clock frequency can decode MPEG1 & 2 Layer1, 2, 3 and MPEG2.5 Layer3, WAV PCM format files and.

VS1011E workflow

VS1011E workflow shown in Figure 2.

　　

　　

Figure 2 decoding chip VS1011E work flow chart

This system, the MP3 or WAV format audio files through SDI bus into chips and decoded.

Decoded, if SCL_AIADDR! = 0, will perform application area code, the code addresses from the address register.

Then, follow the SCL_BASS register (SB_AMPLITUDE bits and ST_AMPLITUDE) settings, data may be sent to the bass and treble to sound processing by the optimizer. Since then, the data volume control unit while backing up to audio FIFO. Audio FIFO maintain data, and as the sampling rate converter and DAC input. Sampling rate converter will convert all of the different sampling rate into CLKI/512, conveying to the DAC. DAC bitwise turn produce stereo analog signals.

Because of this system to lift system, promoting the high-power speaker needs an external power amplifier.

This amplifier is CD4752CZ, the amplifier has a large voltage range and anti-jamming ability, suitable for voltage fluctuations, outside interference strong lift working environment.

Memory organization structure

System uses NAND Flash K9F5608 as storage.

NAND Flash to block (block) and page (page) for a storage unit. K9F5608 including 2048 blocks, each 1 block and 32 pages, 1 page 528 bytes in size, divided into 2 256 bytes of data, and finally the 16 bytes of extra space.

Software design

The elevator runs, if no one went to press, the elevator speech system will broadcast some advertisements, weather forecasts and so on, depending on the requirements associated with dot-matrix or LCD display.

When a key is pressed, the speech system is based on the pressed key value calls the appropriate key handler, such as the number of floors, etc. The main program the flowchart shown in Figure 3.

　　

　　

Figure 3 system flow chart of the main

VS1011E software design

This system audio decoding chip with VS1011E, control processes, as shown in Figure 4.

　　

　　

Figure 4 decoding chip VS1011E control flow chart

VS1011E through a work from model SPI serial bus and host data and control the exchange of information, audio data through the serial data interface (SDI), control data is transmitted via serial control interface (SCI).

VS1011E SPI interface has two working mode: VS1002 new mode (SM_SDINEW = 1) and VS1001 compatibility mode (SM_SDINEW = 0).

When SM_SDISHARED = 0, the control signals and data signal transmission using XCS and XDCS as synchronous signal; when SM_SDISHARED = 1, used XCS as synchronization signal.

As a working model from the machine, VS1011E through a signal line whether to allow the host to Dreq indicates transmission of data, is higher when the Dreq, VS1011E at least acceptable diary SDI data or SCI control command.

Software control points

To control the MP3 decoder should note the following six points:

(1) set up internal control register MODE parameters.

Includes support for file formats, soft-start settings, data flow mode settings, settings and triggered DCLK along the SDI data first place settings, etc. SM_SDINEW and SM_SDISHARED settings here.

(2) if the clock rate is not, you need to set up 24.576MHz SCI_CLOCKF registers.

If by changing the frequency clock SCI_CLOCKF use, you should add the appropriate sample rate writes SCI_AUDATA register, wait at least 11000 clock can only be done after the SPI communication.

(3) set volume registers SCI_VOL; bit 0 to maximum volume, mute, 0xFEFE bits, triggers simulation-0xFFFF electric mode.

(4) to enhance the bass and treble, you can set the register SCI_BASS.

(5) if the use of the user code, by SCI_AIADDR zero turn it off.

(6) the use of RAM-level user code, you can activate SCI_WRAM, SCI_WRAMADDR, SCI_AIADDR to mount these data to achieve the desired functionality.

Conclusion

Based on the MP3 audio systems are now more and more people's attention and affection, they are applied to more industrial fields, such as the bus station name broadcast systems.

Because of its good performance, based on the MP3 audio system in the field of non-professional audio has more widely application. ■