ADSP-BF5619 processing based h.264 video encoder design (1)

0 introduction

H.264/AVC is ITU-TVCEG and ISO/IEC MPEG jointly developed the latest video encoding to international standard, is the image communication research area one of the hot issues.

H.264 video encoding layer (VCL) uses a lot of new technology, making coding performance increases. And previous video codec standard compared with the same bit rate, H.264 has better image quality, this enables H.264 in wireless communications and networks, and other low bit-rate video applications are more widely used. But this is to increase the complexity of costs at the expense of, the H.264 video codec in real-time and transport applications face enormous challenges. With high-performance digital signal processor (DSP) for H.264 real-time encoder is a fast and efficient way, contribute to h.264 video standards promotion and application of rapid. ADSP-BF561 processor performance, with 600 MHz clock speed, and integrated with a common set of digital image processing the peripheral interface, thus providing multimedia and graphics applications to create a perfect system-on-chip solutions. This article is for low bit rate video transmission needs, to research and implement standards-based H.264 video encoding system, while at the same time exploring H.264 software encoder in DSP implementation and optimization methods.

1 H.264 encoding algorithm and ADSP-BF561 introduction

In the actual development process, the characteristics of the algorithms for H.264 and ADSP-BF561 duo structural characteristics, this article has done a lot of optimization work to ensure coding accuracy, dramatically improves coding speed.

The following is a brief introduction to H.264 video encoding algorithm and ADSP-BF561 Duo system.

1.1 H.264 encoding algorithm

H.264 is ISO and ITU jointly developed next-generation video coding standard, with very high compression ratio and very good robustness.

Its overall framework as shown in Figure 1.

In the inheritance of the original video coding standard, H.264 for a number of improvements, including the introduction of 4 × 4 block and sub-block 16x16 9 pattern of intra prediction.

Intra mode of introduction to and transform coding to eliminate redundant spaces, thereby greatly improving the coding efficiency. In the frame mode, H.264 support for size for motion estimation and compensation. The interframe Prediction time block size is not fixed 8x8, but can be from 4 × 4 to 16x16 and ranging including aspect of block (7 types), while supporting multi-reference frame, it can greatly improve the prediction of the performance. In addition, H.264 also uses integer DCT to reduce the amount of computation using Adaptive arithmetic coding to improve code efficiency and can use filter to eliminate low-bit quantization effects of block. In fact, the efficiency ratio of existing H.264 encoding technology can increase by 50%.

1.2 ADSP-BF561 chip structure

ADSP-BF561 is a duo 750 MHz processor, with symmetric multiprocessing (SMP) system structure.

Its SMP structure in signal processing and control features integrated and segmentation can provide higher performance and greater design flexibility. ADSP-BF561 system structure as shown in Figure 2, which contains coreA and coreB two nuclei, each core processing frequency up to 750MHz. Two nuclear has its own independent 32KB L1 instruction memory (16KB Cache/SRAM) and 64KB L1 data memory (32KB Cache/SDRAM), and shareable 128KB L2 memory. Two kernel access different memory, there are significant differences in their rate, with the fastest access to L1, L2 memory, and memory access tablets, and devices are the slowest.

Because access memory rate differences.

Dual-core data exchange among the best in L1 paragraph directly, and the need to use IMDMA controller. The primary function of the DMA controller is in a duo between L1 memory for data exchange between. Use IMDMA controller can access rate slower piece out of memory or on a data processing operation L2, improve data processing speeds, thereby improving the coding efficiency.

2 H.264 video encoding algorithm tuning and implementation

On the encoder optimization mainly on P frame encoding process optimization and on dual-core processing system ADSP-BF561 optimization, reasonable processes conducive to various modules of the independence and integrity, and facilitates later only for the optimization of a module or upgrade process.

And use the duo coordinated handling ADSP-BF561 advantages can further improve its speed.

2.1 P frame encoding process optimization

Because H.264 encoding algorithm compares the huge, optimize program details, in fact, cannot bring about significant efficiency, so the response procedure process itself.

In H.264 encoder JM86 versions, I frames, P frame encoding uses the same module, so you have a large number of intra and inter macroblock's repeat, which enables code to determine the speed restriction. Micro_h264 encoding software model to address this shortcoming, the I-frame, P frame encoding extracted independently coded. But unfortunately, micro_h264 encoding software model to frame the image of the macroblock coding is based on the macroblock in the image of a raster scan order, fails to take into account a macroblock in the frame of the image in different locations have different characteristics, but also for these macro block a unified model for encoding, also produces a lot of judgement criteria, this discourages DSP pipeline operations, nor to the optimization of the module. This article in response to this a disadvantage on micro p-frame codec h264Code processes for optimization.

Based on the macroblock in a frame image location, the location can be on different macroblock coding separately.

At the same time, according to a block in the macroblocks in different locations or may be independent coding.

A frame image is divided into macro block, the different locations of macro blocks have different characteristics.

Therefore, according to a macroblock in the frame of the image in a different location to classify the macroblocks to will have the same encoding properties of the macroblock is classified as a class, so that you can set the frame image of macro blocks divided into five categories. Figure 3 shows the macroblock classification figure.

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