Digital network video monitor multi-channel transfer logic design (1)

Summary: this article is to introduce in the video control panel in the multi-channel video signal input cases in the data cache, the design of the signal format conversion, and Altera's Cyclone device implementation of the entire process.

Includes simple introduction video monitor circuit principle, this transfer logic in the system and status, and details the logic implemented using FPGA design.

As technology advances, the video surveillance market has been developing rapidly.

Video surveillance with its intuitive, easy, and information content rich and widely used in many occasions. In recent years, with the Internet wide popularity and computer, network, and image processing, transport, technology, video surveillance technology has come a long way. Video surveillance has penetrated to the education, Government, entertainment, hospitals, hotels, stadiums, urban security and many other areas, video monitoring server is called following the phone after another tremendous market and development prospects of consumer electronics products.

Digital network video monitoring server key from the camera gets the analog signal to digital compressed and sent to the network, its principle diagram shown in Figure 1.

Figure 1 digital network video monitoring server principle diagram

As shown by Figure 1, monitor circuit board mainly consists of A/D chip FPGA chip multi-channel transfer, compressed chips, CPU, etc.

Where this article is to introduce multiple transfer logic FPGA chip at A/D and compression chip, due to the FPGA internal PLL module contains, so connected with the FPGA chip TW2804 27MHz input clocks can be produced by the FPGA.

Altera's Cyclone here selection series, its internal EP1C6Q240C8 90k storage capacity, 6kLEBS, 2 PLL, behind the design, will speak to the entire design to 64 k of storage capacity, one PLL, approximately 4 — about 5k LEBS, so use this low-cost FPGA, you can complete this design, and basically fully incorporates the most resource inside, plus this chip PIN 240 and can meet outside of the pin connection, Altera's EP1C6Q240C8 become the logical design of the best selection of devices.

As shown in Figure 1, A/D chip from four camera Quad analog video signal, use the TW2804 chip Techwell Inc, this chip supports four channel video analog signal input, the output is a digital signal ITU-R BT.656 format, the clock is 27MHz.

D1, D2, D3, D4 signal timing diagram shown in Figure 2.

Figure 2 ITU-R BT.656 format signal timing diagrams

With EAV and SAV were endline and costumes flag signals, among them are the rows and rows of blank signal, SAV subsequent VALID valid signal to the d1 format 1440bytes effective video signal, the signal of these together is the video signal of the line signal, a frame of video signal including the 576 lines such rows signal, which is valid in this format frame output video signal 1440 * 576bytes signal, since each row signal consists of two bytes to represent a pixel, so the d1 format frame of pixels as 720 * 576 resolution.

FPGA transfer logic to achieve the functionality to display Terminal simultaneously displays four video signals.

That is to be displayed as shown in Figure 3 the video signal.

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