Aerospace embedded image processing technology

Aerospace times not only facilitated the launch vehicle technology, application of satellite technology and deep space exploration technologies, but also the foundation of Internet development into space-space network that extends to the $ 2 million km of Mars, contributed to space-based embedded image processing technology, and other aerospace microelectronics applied technologies.

Embedded image processing technology

Space-based embedded image processing features are: one is embedded, volume, weight and power consumption is very high; the second is the complexity, to deal with G-class pixel frame; three is reliability requirements meet the poor working environment, long service life; the fourth is real-time, the second-level calculation time.

In order to implement these features, you need from aerospace embedded computer function, structure, and physical implementation of the three aspects of the research.

(1) unified architecture model

In order to satisfy increased chip integration and shorten the design cycle, to IP-based design platform technology and architecture from a functional to a collaborative design approach has been developed.

Due to the non-control flow computer architecture complex, inefficient, and now the computer architecture is the architecture of the control flow, follow our computer architecture of classification model, control flow architecture can be divided into three categories: one is based on the architecture of the instruction stream, which is represented by the microprocessor architectures, according to Flynn adopts directive flow and data flow two logical concepts of total SISD, SIMD, four MISD, MIMD architectures; the second is based on the data flow architecture, also be with ASIC (such as Systolic array) circuit represented architecture because it only stream concept therefore only two types of SD and MD, because although the ASIC circuit efficiency is high, but in order to overcome this drawback does not have a processor flexible, there have static programmable FPGA circuit; the third is based on the structure and order flow (Configuration Stream) architecture that is commonly referred to as reconfigurable (Reconfigurable) architecture, which is the dynamic programmable circuit, total SCSD, SCMD, MCSD, MCMD four categories.

These classification by logical concepts of architecture can be combined to use, its options can have 1023.

In relation to the specific implementation of programmes more, for example, different manufacturers of processor instruction set is not the same.

While the features and architecture of collaborative design that is functional to the architecture of the map, in order to ensure that this mapping of efficient and uniform, presented a unified architecture model, from the three aspects of a unified architecture: first presented a Unified _ISA model, as shown in Figure 1, the above three architectures from the directive on the harmonization of the collection; the second is a set of advanced language and assembly language packs in the middle of the map language, can be advanced language compatibility and readability, and assembly language program is efficient and mapped directly of unify; three is through an intermediate mapping language programming, software components and hard Widget Design.

Figure 1 Unified _ISA model logical concept map

Specific to the instruction stream architecture, its SISD, SIMD, four MISD, MIMD architectures instructions child collection is consolidated into SISD architecture collection of instructions, for the data flow and structure the flow of architecture is by increasing the corresponding directive into directive SISD architecture; in other words, a collection of diagram 1 in SIMD, MIMD, ASIC and RC Unit four MPP Device are accessible through the software component description.

These software components are available in SIMD or MIMD architectures executed directly, or can be automatically mapped to ASIC or RC circuit of the Device.

(2) virtual array of parallel computing

Because of the G-class pixel frame remote sensing image processing needs, MPP parallel computing array has been developed, because the image frame is two-dimensional, the corresponding processing element array is two-dimensional, as shown in Figure 2.

Although the chip integration is already very high, but still not on a chip for G-pixel frame G a processing element of the array, and now also only use WSI technology completed million processing element of the array. Therefore, you can only use virtual processing element array technology to address the MPP programming convenience and readability of the program itself. In other words, the MPP image processing program is based on virtual parallel computing array design, MPP program design, always assume that the figure 2 grid array of the values of M and N is the number of dimensions of the image frame size equal to the actual processing element array size is much smaller than M×N m×n, MPP program is automatically mapped to actual processing element array. For image processing algorithms, image processing array MPP is usually calculated as SIMD architecture design. The appropriate design issues: the location of the address element PE represents the location choice, using PIM design solution to image processor and image memory bandwidth issues, as well as parallel resampling.

Figure 2 virtual processing M×N $ array

(3) the physical implementation of the Bionic

The mysteries of the universe and the brain, stimulating human space travel and human journey, so that the embedded computing technology from traditional computing model, developed to autonomic computing model, to a natural computing mode.

Traditional computing chip technology is now under a single functional chip development to multifunctional SoC chips of the new phase, the software technology from structured programObject-oriented design, to programming, to Component-based programming as well as to Agent-based programming.

August 1956, John. McCarthy's first introduced artificial intelligence (AI, Artificial Intelligence) concept, then he said: "the thought of the machine will not 20 years to come", but now also at an early stage of artificial intelligence, cognitive science, "only" and the expert system was a success, this illustrates the difficult artificial intelligence.

It is estimated from the 201X years, 200 x will be entered in the electronic age of NA 30nm, robot autonomous mobile operation, gravity walk and airflow, as well as fish-eye lens for shooting and Autonomic Computing bionic technology will be more perfect. Autonomic Computing's bionic technology at present mainly from the use of fuzzy logic reasoning ability, neural network learning ability and gene computation capacity expanded research work, but the real challenge is to change and to redefine the nature of computing hardware.

In many ways, the human body is one of the most effective computer, the nervous system in the human body is the result of NA (Sodium Na) and potassium ion (K, Potassium), ion movement throughout the brain and nerve centre of the body between the signal and from the brain to interpret and process, which governs the activities of the human body.

It is estimated that from year to year 20XX 201X will step into the electronic age of NA 10nm for quantum computation of self-assembly technology, chemical calculation of DNA technology, and fault-tolerant computing neuron technologies natural computation of bionic technology development. Especially the molecular self-assembly technique, already achieved lab chip (ALM), practical results.

Closing remarks

To sum up, we feature presented a unified architecture models, from structural design to effectively support virtual parallel computing program design of processing element array, from the physical implementation will study a supported self-assembly technology design platform.

In short, SOC, nano-manufacturing and independent charging technology, will further contribute to the space age embedded image processing technology development.