The G.723.1 based TMS320C6201 speech codec implementations

Current overIP, Voice (VoIP) technology is growing popularity of voice traffic over the Internet is also growing.

Currently used in VoIP low bit rate voice compression standard G.729 G.723.1 and mainly in two ways. With the continuous development of VoIP technologies, product integration and performance further improved, the use of a new generation of high-performance DSP, realization of single-chip DSP processing multi-channel voice signal, is the future trend of development. This article according to the characteristics of C6201 chip, made a lot for the optimization of the G.723.1 standard itself, reducing the volume of operations, meet the real-time multi-channel signal.

1 the g.723.1 standard introduction

ITU G.723.1 standard for the organization in 1996 introduced a low bit rate encoding algorithm.

Mainly used for voice and other multimedia sound signal compression, such as videophone systems, digital transmission system and high-quality audio compression system, etc.

G.723.1 standard in two 5.3kbps 6.3kbps and bit rate.

Where high bitrate algorithm has a high voice quality, and the reconstruction of low bitrate algorithm of calculation complexity is low. And general low bit rate audio coding algorithm, G.723.1 standard uses linear predictive analysis method of synthesis (Analysis-by-Synthesis). To quantify the excitation signal, high bit-rate algorithm with multiple pulse quantitative maximum likelihood (MP-MLQ), while the low bitrate algorithm then uses the arithmetic code excited linear prediction (ACELP). Currently, G.723.1 has been able to achieve a variety of DSP chips, such as the United States TI company TMS320C5x, TMS320C54x and Lucent Technologies company DSP16xx, etc.

G.723.1 codec can remark by 8kHz sampling audio signal compression, its structure diagram shown in Figure 1 (a).

As can be seen from the figure, the encoder is based on linear prediction analysis method, its purpose is to minimize the perceptual weighting error signal. In order to reduce the bit rate, G.723.1 takes longer to frame size, frame 240-like values, i.e. 30 Ms frames long. Each frame the input signal is first of all by a band-pass filter to filter out DC component, and then be divided into four 60-like value child frames, each child frame independently LPC analysis. In order to improve the LPC coefficients of continuity, with a length of 180-like value of overlapping Windows, that is, both before and after two child frames, which make the algorithm introduced in 60-like values ahead of time, so the total delay for algorithm 37.5 milliseconds. LPC coefficients using linear spectral frequency (LSF), LSF parameter uses the forecast split vector quantization, only the first four frames. In order to improve the quantification of perceived quality, high-pass filtering of voice signals through the perception of weighted formant filters and resonance peak noise shaping filter to generate the initial target signal. The first parameter of each child frame does not quantify the LPC coefficients, the latter through every two child frame to get open-loop pitch estimated, in which the pitch range from 18 to 142-like value. LPC synthesis filter, formant perceptual weighting filter and resonance peak noise shaping filter used for the calculation of zero input response system and the best incentive is estimated. G.723.1 codec also includes a five-pitch Predictor, the argument based on the open pitch estimates and impulse response for closed-loop pitch search. The best incentive is estimated at from initial target signal subtracted system zero input response and pitch Predictor contribution to achieve the ultimate goal of the signal, and then for high and low bit rate using MP-MLQ and ACELP method to quantify. Where LSF parameter, pitch and incentive argument passed to the decoder required.

The first by the decoder is LSF synthesis filter parameters reconstruction LPC and, depending on the pitch value and incentive argument be adaptive Codebook stimulus signals and fixed code this excitation signal.

In order to improve the quality of the voice of subjective reconstruction, the decoder also includes a filter, the filter after the formants and pitch after filter. Excitation signal loop through pitch after filter, synthesis filter and formant synthesis of reconstruction after the filter, its structure diagrams for speech is shown in Figure 1 (b).

　　

2 introduction to TMS320C6201 chip structure

TMS320C6201 is a 32-bit fixed-point DSP, operating frequencies up to 200MHz.

It has two sets of arithmetic unit, each group of 4, 8. In addition to the M-unit can only make a multiplications, other cells can be flexible in use, such as D unit can do Load, Store, and subtraction operations, S unit can be shifted and the addition and subtraction. C6201 32 General-purpose registers, divided into A, B on both sides. Both sides of the registers have crossed paths, the same directive can simultaneously access the double side of registers. C6201 adopts VLIW architecture, a maximum of 8 command executing at the same time (each unit). It has an 11-level water, all the instructions are reduced instruction. C6201 allows the use of cache (Cache) mode, you can run large programs without reducing speed. Figure 2 is a C6201 structure.

　　

3 standard implementation

Use the g.723.1 standard C6201 realize the greatest advantage is its strong parallel processing capability, using a DSP can achieve multi-channel voice compression, greatly simplifies hardware design.

C6201 is TI introduced the first support C compiler's DSP chip. Typically, the c compiler can complete the entire work of 70 per cent and 30 per cent of further optimization must be achieved through handwritten compilation, so on the whole program optimization into C language and assembly language level in two parts.

3.1 c language-level optimization

3.1.1 loop unrolling (loop-unrolli

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Use with parallel capacity of DSP development software, an important idea is to make full use of DSP word length and a large number of arithmetic unit, try to start the loop body.

By increasing each loop is the number of instructions executed to reduce the total number of loops in the same clock cycle to run more orders, increase the efficiency of the loop.

DSP chip inside of arithmetic unit operating efficiency is very high, but if you register and data bus data exchange between frequent, will enable DSP execution efficiency.

Because the DSP in memory operations often requires several cycle delay, such as Load instruction to have 4-cycle latency, Store instruction requires 2 cycle delay. In order to reduce the time-consuming memory operation, you can enter in the program, before the loop body will frequently used data in the register, and then repeatedly call practice proved that this method can improve the efficiency of the part.

3.1.3 use intrinsic functions (Intrinsic)

The inner function was in some C6201DSP assembler instructions with "___" constitute it can easily achieve certain required several C statement to implement functionality.

It is a very simple and effective optimization method, it calls the C function format and ordinary, but at compile time, the compiler automatically adds Intrinsic with the corresponding assembly instruction. C6201 directive set the vast majority of arithmetic and logic directive can use, such as saturated with absolute value, saturation, saturated subtraction, saturating, two words in the corresponding half-word at the same time plus or minus, two words in the corresponding half-word while travelling or cross multiplication, normalized and bit operations, etc. After this step in the optimization, the majority of the loop body can generate more effective running kernel (piplinedkernel). Using Intrinsic alternative G.723.1 original c code, the operation quantity down to 1/10.

3.1.4 on some reasonable redundancy of streamlining

After inspection, found ITU-T G.723.1 c code there are redundant.

Like 6.3k code rates MP-MLQ search module, you only need to even location impulse response of autocorrelation, odd position of impulse response since the relevant calculation can be omitted.

In addition, g.723.1 standard in quantities of 10-10-order FIR and IIR filter operation, such as coding portion perceptive weighted, zero input response and decode part of comprehensive filter and after filtering, FIR and IIR's universal form can be expressed as:

Each loop, fir filter memory with new input values updated IIR filters memory you want to use the new output value is updated, use standard provides algorithm, to dedicate a 10-step cycle update memory.

If you use a 10 unit size of circular buffer each time a new value overwrites the oldest sample values, dynamically adjusting loop buffer head pointers, you can save the original update for memory cycle.

3.2 compilation-level optimization

Because the c compiler only 70 percent of the work done and for complex loop C compiler cannot generate efficient code, and so on operation of large module can only be compiled with handwriting.

3.2.1 word length optimization

C6201 word length as a 32-bit, it supports by byte, half-word, Word, access.

For 16-bit array, when it is arranged in memory sequentially, using 32-bit when reading and writing instruction LDW or STW substitute 16 bit literacy instruction LDH or STH, cycle times can be reduced by half. In addition, the assembler instructions support C6201 two 32-bit registers in the upper 16 bits and the low 16 bits of the result of mutual travel between, respectively, into a different register, do not affect each other. Specific instructions for SMPY (L×L), SMPYH (H×H), SMPYHL (H×L) and SMPYLH (L×H). Through the word-length optimization, can greatly improve the program's operating efficiency. It should be noted that, in using the word length optimization, arrays in memory must be aligned on 32-bit boundary.

3.2.2 external loop optimization

The C compiler C6201 on multiple-circulating the innermost General can better optimize to one to two sentences, but the external cycle optimization efficiency is a lot worse.

Handwriting compilation, you can expand the internal circulation, then turn the outer loop directives into one, you can reduce the cost of the cycle.

C6201 loop General leading (Prolog), kernel (Kernel) and emptying (Epilog) three parts.

Code parallel degree from Prolog began rising parallel degree within the Kernel, Epilog and Prolog instead, parallelism. In multiple-circulating, if you try to put a leading part in the cycle of instructions and fill in the empty portion of unused units together, you can perform this cycle of emptying the statement at the next cycle of the statement. This can not spend the entire loop cycle and increasing efficiency.

4 achieve results

After c-level and the level of optimization of assembler, finally realized all the G.723.1 codec takes the entire code 10.6MCPS, program space for 208K byte (program includes some c6201 library function), the data space for 8K byte, Codebook size 20k byte, multi-channel context data to 1.48K byte.

200MHz of C6201 per second can real-time codec 16-channel voice signals. All code all passed the test of the test vector ITU-T. Table 1 is the main module of the computation.

Table 1 G.723.1 amount in principal module operation

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This article by utilizing a C6201 DSP ITU-T G.723.1 full duplex real-time multi-channel voice codec implementation.

The implementations can in IP telephony, video conferencing has been widely used.