FPGA in frequency synthesizer application design and circuit (1)

Overview

In recent years, the rapid development of the integrated circuits for digital circuit research and application of a very large space for development, FPGA low power consumption, high reliability, small size, light weight, low prices, a user can repeat defined logical functions that have the characteristics of a repeatable programming and, therefore, the FPGA allows digital circuit system is designed to be flexible, and greatly reduces the development cycle of the system, reduce the volume of digital circuit system and reduce the use of chip.

FPGA has been widely used in communications, radar, navigation, radio, television, instruments, automatic control and computer, etc.

FPGA design flow and design environment

Figure 1 indicates that the entire design process FPGA, enter from the design to the device programming of the four stages to MAX + PLUS II provides environment to complete.

Correspondence with Figure 1, Figure 2 is MAX + PLUS II provides the design process.

　　

Design input

MAX + PLUS II input can have three methods, i.e. graphic input, text input and waveform input.

Graphic input or input circuit schematics, not only can you use MAX + PLUS II in rich graphics device library, but you can use almost all standard EDA design tools. If identifiable criteria EDIF netlist files, VHDL netlist files, OrCAD schematics and Xilinx netlist files, text input method support for ALTERA corporate language, while compatible AHDL VHDL and Verlog HDL. Waveform enter most features, it allows the designer to edit the input waveform, and the system automatically generates the function module.

In addition, the symbol editor used to edit your own module symbol.

By underlying editor you can see the actual device's internal structure, and can change your device pins distribution, or adjust the various modules in the device's internal macro cells between distribution, thereby optimizing the device performance.

Design implementation

Design means that the selected FPGA internal physical realization of the necessary logic, this process with MAX + PLUS II in the heart of the compiler (Compiler) is complete, it is mainly based on the design of the input file is automatically generated for device programming, waveform simulation and delay analysis required data file, include the following steps:

① Select target device and set the compilation environment parameters, the step from circuit designers to design, the following steps are performed automatically by the system.

② generate individual modules of binary netlist (.cnf) file.

③ connect all the CNF file, setting up a database describing the entire design.

④ for logic synthesis, calculate all Boolean equation, and optimize the triggers design.

⑤ the entire design is mapped to the corresponding device.

⑥ generated waveform simulation files and program files.

Design simulation

Emulator and delay Analyzer use the compiler-generated database file automatically complete logical functional simulation and delay performance simulation.

In the simulation file load different excitation signal, you can observe the intermediate results, and output waveforms. If necessary, you can return to the design phase, and modify design input, ultimately meet the design requirements.

Device programming and testing

The result is correct, you can make the device programming through programmer BYTEBLASTER cable will download to a practical chip design, final test chip in the actual operating system performance.

Device performance

Component diagrams

EPF10K10 internal block diagram shown in Figure 3.

　　

Device resources

ALTERA Corporation launched a 0.25 μ m CMOS ROM procedure specification of the structure of good performance, high density FLEX10K series devices products, chip door number has reached 25 million, its resources, such as table 1.

Device speed

Selection of EPF10K10 already meet the requirements of the frequency synthesizer, its speed rating as table 2.

　　

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