FPGA and DSP for high-speed communication interface design and implementation (1)

In radar signal processing, image processing, signal processing in real-time is critical.

Due to the FPGA chip in large data volumes underlying algorithm processing advantages and DSP chip in complex algorithm processing advantages, DSP + FPGA real-time signal processing system is becoming more and more widely. ADI's TigerSHARC DSP chip floating-point processing series of superior performance, based on this class. DSP FPGA DSP + handle system is widely used in the complex field of signal processing. At the same time in this kind of real-time processing systems, FPGA and DSP chip for real-time communication between data is critical.

TigerSHARC family of DSP chips and external data communication mainly in two ways: bus and chain junctions.

Chain intersection approach is more suitable for FPGA and DSP real-time communication between. With the real-time signal processing operations of a growing number of DSP parallel processing is widely used, they share the bus each map storage space, and FPGA by bus connection, which will inevitably lead to FPGA and DSP bus competition. Both bus and FPGA, DSP, cable PIN many uses FPGA I/O pins too many resources. Communicate intersection with chain not only effectively alleviate the pressure on the bus DSP, and transmission speed, and the connection between the FPGA is also much less, so the chain junction way more appropriate for FPGA and DSP real-time data communication between.

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Examination of the literature [3] gives TS201 performance comparison with TS101, but not for both chain junctions are described in detail, this article on both chains crossing was detailed analysis and comparison.

Literature [4] the design of the collection system, DSP and communication FGA is limited to the FPGA, TS101 of Simplex communication; document [5] gives the FPGA internal no meter TS101 chain junction block diagrams, but only gives a simple introduction to give designers to reference. This article uses Altera Cyclone series chip company EP1C12 implements and TS101/TS201 two chip chain junction duplex communication, and provides specific design implementation. Which the design has been successfully TS101 applied to a signal processor.

1 chain TS101 and TS201 intersection analysis and comparison

TS101 and TS210 are high performance floating point processing chip, both are widely used in the complex field of signal processing.

TS201 is after the launch of the new TS101 chips, nuclear clock up to the various 600MHz performance is relatively better than TS201-TS101 and adopts low-voltage junction chain differential signal LVDS technology, low power consumption, noise and better performance. Table 1 lists the two chips chain performance comparison of detailed road junctions, which work in TS101 nuclear clock 250MHz, TS201 nuclear clock work in 500MHz.

　　

　　

Limited to the length of the chain TS101, TS201 junction structure see references [1] [2].

Because TS101 transceiver side sharing a channel, you can only achieve half-duplex communication. And made the transceiver-TS201 two independent channels, can achieve full-duplex communication, theoretical data transmission speed can be doubled. Although the chain junction TS201 and receive channel independent, but in fact both sending and receiving mechanism largely the same, are relying on the transceiver cache and shift registers and receive data. However FPGA internal design of the chain without having to stick to a junction, as long as you comply with the chain junction communication protocol and communication.

2 FPGA and DSP chain crossing communication

2.1 chain crossing communication protocol analysis

A total of chain junction TS101 11 root pins, through 8 root data cables (LxDAT [7 ..0], where x can be 0, 1, 2 or 3, the representative TS101 or TS201 0,-3, a link, following his mouth with) for data transmission, and adopt 3 root control line (LxCLKOUT, LxCLKIN, LxDIR) to control the data transfer clock, communications of the grip to the direction and data transfer.

Which notification chain junction LxDIR to current working status is received or sent by the output pin that can left vacant. TS201-chain Junction 24 root pins, receive and send all 12 root pins, through LVDS forms of data cables (LxDAT_P/N [3 ..0]) and clock line (LxCLK_P/N) for data transmission, and adopt LxACK and LxBCMP # (the ' # ' represents the signal low effective) to notify the receiving ready and block transfers.

Using FPGA and DSP through the chain of communication is the key at the sides of the handshake signal communication, promote the transfer of data.

In fact, if you consider the LVDS signal form TS201 has been converted, the TS101 and TS201 chain road transport data form is the same, are triggered by the clock dual DDR data along, and each time the number of data transferred is 4 long Word (i.e. 128bit) integer times. In the light of the above two chip chain data in common junction, so using FPGA and two types of chip communications, receive and send data to cache part of a design should be very similar, the only communication design part of the handshake signals should be considered separately. The following respectively.

2.2 FPGA-based design TS101 chain junction

Figure 1 shows the FPCA and TS101 for half-duplex communication design at the chain (on LxCLKOUT, LxCLKIN are FPCA point of narrative), the interface by the receiving, control, and sent three parts.

The design of FPGA clock 40MHz, TS101Nuclear clock on a junction in 250MHz, chain clock set to 8 DSP core clock frequency, FPGA and DSP for actual data transfer rates for 62.5MBps.

　　

　　

(1) receive parts: from coding and cache of two parts.

Because chain number wrong is the junction of DDR form, not convenient data cache, this article uses QuartusII Megafunctions altddio module in the rising edge data and falling edge data separately. Note that this module to drop along the data export will lag behind the rising edge data in one clock cycle, the output should use chains crossing clock signal (LxCLKIN) through the D flip-flop to align the data. The module inclock must use chains crossing clock signal to ensure that the data properly read, as shown in Figure 2. And because the DSP internal data is 32-bit long Word, so write to receive cached before it should be enclosed within a set D trigger will data aligned here note 32bit DSP chain junctions to transmit 32-bit data in the low 8 bits.

　　

　　

(2) control part: from token conversion module and control modules, is a core part of the entire design, complete the sections of the control and communicates with the FPGA internal (via CTL group signal).

Communicate intersection of chain TS101 handshake is relying on two root clock signal authentication token instruction complete, that is, when the send-side were formerly high LxCLKOUT signal for low level, as a token request sent to the receiver. If the receiver is ready to receive, receive-side LxCLKIN; if a token issued by six clock cycle LxCLKIN signal is still high, the shoulder moving data transmission (above the clock signal to send-side perspective). This design, the token conversion module is responsible for validating the token and sends the token. Here it should be noted that because the authentication token low level number of the clock signal (PLL_32ns) is an FPGA clock (CLK) through the PLL multipliers, and DSP chain junctions, asynchronous validation token when the counter counts to five low level can be considered to achieve communication handshake, you may lose data. After reaching the handshake control module to receive notifications or send the cached output control signal, which receives control signals including write cache clock and write-enabled. Send control signals including read cache clock, reading to and [1] [2]