Based on the Verilog hardware description language of the AES algorithm (1)

Introduction

Password module is a security system is an important part of its core task is combined with the/decrypt data.

At present, the AES block cipher algorithm to its high efficiency, low cost, simple, and other characteristics are widely used in password module. As computer information technology and VLSI technology matures and development, through hardware to implement key internal operation of the module, you can ensure that the outside world without key flow of plaintext, to achieve a real sense of confidence. In addition, the hardware implementation also has high speed, high reliability characteristics. Many current hardware implementation of AES algorithm uses a lookup table based on the RAM to implement algorithms in one of the most critical part of SubBytes. This article uses the composite domain to achieve SubBytes operation part of inverse for easy use of combinational logic reduces the area. At the same time using encryption/decryption operation column transform part of the circuit for reuse, further savings in realization of the area. This enables AES password applied to RFID systems, IC card, etc., area requires smaller occasions.

1 Introduction to the AES algorithm

The AES algorithm is a block cipher iterative type, its packet length and key length is variable, each can be independently assigned to 128 b, 192, 256 b b.

This article primarily discusses the packet length and key length of 128 b. The AES algorithm is to enter the plaintext (or redaction) into 16 bytes, Add in the first Round after 10 Keys transform round. Iterative process is identical to the former 9 rounds, after bytes instead (substitute bytes), line-shift (shift rows), columns of mixed (mixcolumns), rotation keys plus (add round keys), the last round of skip a column mix (mix columns). Decryption and encryption process is similar, but the execution order and description of the content is different, therefore the AES algorithm for encryption and decryption operations are required.

2 AES hardware design

According to the AES algorithm theory and basic structure, the entire AES algorithm module is divided into four relatively independent sub modules: interface module, control modules, encryption and decryption operations module, key expansion module.

This article is designed to have the password algorithm does not include key generator, with the key passed by an external input interface module, the decryption operation data output via the output interface. The AES algorithm module is the overall structure as shown in Figure 1.

2.1 interface module design

Input interface module's main task is: will data to the encryption and decryption operations module, place the imported key delivered to key expansion module.

As clear text and key input is 128-bit, will cause the entire module input/output too much, take too many resources, taking into account the design of this article is mainly applied to the area requires smaller occasions, such as RFID systems in data transmission, that is, each time the data transmitted is 64 bits, so the use of four 32-bit registers, under the control of the clock every time 1 group a 32-bit, four clock cycles can be 128-bit data, can effectively reduce resource consumption. Output interface modules is 128-bit decryption result output, also take the 32-bit 4 group output method.

2.2 control module design

Control module's main task is to implement encryption/decryption operations module and key expansion modules work started.

Control module in clock pulse control, production control encryption/decryption module byte substitution, transposition, columns, rows, mixed with various parts of the work of the key. Can be one of two State of the State of the machine controls. When new data or key input signal through the state machine can determine last encryption/decryption operations are completed. If a state machine signal is busy, the decryption operation is in progress, need to wait for; if the signal is idle, the decryption operation is complete, you can start the encryption and decryption operations module and key expansion module, enter the data and the key to the encryption and decryption operations module and key expansion module, start a new set of data encryption and decryption operations.

2.3 decryption operations module design

AES algorithm round transform features the hardware implementations can have more than one way: serial manner, wheel transform can adopt combo logic implementation; in 10 round, first round results directly as input to the next round; and in 1 cycle completes one grouping operation that make the best throughput.

But it requires a large amount of memory resources and combinational logic resource support, General FP-GA chip to meet the capacity requirements, and the clock frequency is very low; basic iterative feedback, all iterations using only one wheel transform module, and 10 clock cycles to complete one grouping operation that takes up less resources; wheel assembly line, insert the wheel transform, each register operations into multiple operation segments, each clock complete 1 operation, the advantage is you can improve the algorithm running clock frequency. But the wheel at all levels of water part cannot be executed simultaneously, which increases the number of clock algorithm. Wheel assembly line of progression, the more the number the more clock, although the algorithm can achieve very high frequencies, but did not significantly improve the throughput.

The comparison shows that IMIS, this article on the AES algorithm implementation aims to minimize resource consumption, minimize the area.

It uses basic iterative feedback work design.

2.3.1 SubBytes () and the design of InvSubBytes ()

Bytes instead of the entire AES hardware implementation of the most important transformation, in the encryption and decryption operations module and key expansion module bytes instead of the main operation process.

Therefore, byte instead of hardware design determines the entire AES algorithm for hardware implementation of speed and size. Bytes instead of by a lookup table and be of arithmetic operations. Tradition of the AES algorithm with lookup table methodsRealization of bytes instead, you can improve the speed, but the inverse of the transformation input data as 8-bit, encrypt and decrypt the replacement byte table is different, so the selector and the register number, the hardware implementation of larger, it is mainly used for high-speed AES implementation. Arithmetic operations in hardware design performance for combinational logic, using the arithmetic operation of hardware design is to reduce complexity, decrease the area.

2.3.2 ShiftRows () and the design of InvShiftRows ()

Line transfer transform function in the intermediate state of the row, the rows in the State according to different offset for circulation.

Cryptographic operations intermediates of 0 ~ 3 rows, respectively, to the right loop mobile O, 1, 2, 3 bytes. This action is only carried out according to the data, hardware bytes when you only need to make adjustments on the wiring, Basic does not occupy the hardware resources.

Decryption process is just the inverse of the line shift, move to the left circle, respectively, 0, 1, 2, 3 bytes.

Similarly, the operation is only the data in bytes. If you have a location change, bytes can now be modified on the wiring.

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