Summary: presents a new raster displacement sensor 4 Sub-frequency circuit design method. the use of programmable logic devices (CPLD) has designed a new segmentation module, using Verilog HDL language to write four multiplier segmentation, identification and counting module program, and simulation. simulation results show that, compared with traditional methods, new design for short development cycle, high integration, modular and easy to modify.
Keywords: grating displacement sensors; four multiplier subdivision; programmable logic devices (CPLD)
Grating sensor is based on the moire measuring sensor, to improve its measurement resolution on raster output signal processing is a necessary link broken. in practice, usually four multiplier methods to improve positioning accuracy £ ® four multiplier circuit and sentenced to the circuit is designed as a whole, as four multiplier and sentenced to four circuit. to achieve the multiplier circuit structure, but in application discovery, because some four multiplier circuit of precision or stability is not high, so that the sensor performance degradation. authors of several common four multiplier circuit, on the basis of the application for a different, designed two different four multiplier circuit scheme and on the two programmes of structural and use methods were compared and simulation.
1 four multiplier circuit design principles
Grating sensor output 2 channel phase difference as A square wave signal by 90 and B. as shown in Figure l, A, B, both confident pulse number represents the amount of displacement of grating, marking the grating at the forward and reverse movement 4 multiplier of signal, the counter counts back into the relative position of the counting process generally-in two ways: first, the internal timer counter by microprocessor for count; the second is the realization of reversible counters on the forward and reverse pulse count.
Grating signals A, b has the following relationships.
① When grating forward movement, raster output of A signal phase advance B phase 90, in a cycle, two believe, a total of 4 times relative changes: 00 → 10 → 11 → 01 → 00. Thus, if you change every occurrence, realizing an up-down counter will increase the count, a cycle of 4 plus can be achieved, thus achieving positive count go status four times the frequency counts.
② When grating reverse move, raster output of A signal phase lag in signal 90 B, then a period of two to believe, there are 4 relative changes: 00 → 11 01 → → → 00 10. Similarly, if you change every occurrence, realizing CNTR will reduce count at a time, in a cycle, a total of 4 times reduction can be achieved, the count for reverse
Status four times the frequency counts.
③ When line disruption or failure, there may be other State conversion process, this counter is not counting operation.
The above analysis, it is possible to make the processing module state transition diagram (see Figure 2), where the "+" and "-" to indicate counter plus/minus 1, "0" indicates that the counter is not an action.
2 traditional analog circuit segment
Traditional double frequency count circuit shown in Figure 3, which consists of grating signal detection circuit, identified the location of the broken circuit, 3-part count circuit. grating signal detection circuit consists of a phototransistor and comparators LM339 composition. from grating moire irradiation to the phototransistor Ta and Tb, their output signals to two LM339 comparator are inputting port, a signal from an LM339 output voltage Ua, Ub plastic evacuation to identify to the circuit, the data entry chip-7495-Dl receive Ua, Ub, D0 received by SCM received pulse ALE-supplied. and then signal through and Y1, Y2 and door or gate E1, E2, E3, consisting of the circuit to be 2 tablets 74193 concatenation of 8-bit counter. SCM by P1 port receives 74193 output 8-bit data, resulting in a raster position.
Use these designs, often need to add more programmable counter circuit components numerous, complex structures, and power consumption increases, decreases stability.
3 the grating based CPLD, four segments identified to the design of the circuit and counter
Using CPLD grating sensor signal processing diagram shown in Figure 4, Figure 3, the three parts of the simulation of logic circuits full integration in a CPLD chips, achieve high integrated. working site of interference signals allows the grating output waveform distortion, pulse signal through 40106 Schmitt trigger, and RC filter shaping and then fed into the CPLD, CPLD on pulse signal counts and sentenced to and enter data into internal registers.
3.1 CPLD chips choice
ALTERA CPLD chips use the company's MAX7000 family of products, the chip has EPM7128S high impedance, electrically erasable, in system programming, and other characteristics, available gates to 2 500, PIN between the maximum delay is 5 μ s working voltage of + 5 V. simulation platform with ALTERA Corporation Q U A R T U S Ⅱ development design.
Distinguishing four 3.2 subdivision and the circuit
Four segments and identify the module logic circuit as shown in Figure 5, using global clock crystal oscillator produces 10MB CLK, assuming that signal A ahead of representatives indicates that the grating when B towards a direction of movement, A lagging B says gratings in the opposite direction signal B mobile .A, respectively the first level after the trigger becomes A D ', B ' signal, then by
A second level D after becomes A trigger ", B" signal to trigger signal .D plastic, eliminates input signals of sharp pulse effect on subsequent multiplier circuit no longer use the original signal A, B, improving system performance in four times the frequency of the circuit, using combination of sequential logic devices on A ' B ', A "B" signal for logical combinations of two-channel output pulse: when A ahead of B, ADD the count pulse, MIMUS maintain high level; on the contrary, when A lagging B, ADD a high level, MINUS to minus count pulse.
Comparative figure 5 and Figure 2 you see that a new design method using the number of the device significantly reduced compared to traditional methods, so the power consumption significantly reduced module-system wiring in chip internal implementation, anti-interference. due to the use of a programmable logic devices, system modifications and upgrades only need to modify the associated program statements, and needless redesign hardware circuit and the production of printed circuit board, allowing system upgrades and maintenance convenience greatly increases.
4 four multiplier circuit simulation module for subdividing
Figure 2 shows the State transition diagram, use HDL Verilog hardware description language to describe the circuit features, programming ideas for A, B a time signal values of status as a state judge flag state, and placed in registers, when A prestate. B any status change, the state value is changed, this time the state value is compared to the time of prestate, the can under A, B two pulse relative change of status to determine the count value of plus or minus, that db counter output value of plus or minus sign.
The simulation results as shown in Figure 6. when the signal A jump ahead along the B, count value db forward count; when A jump along the lagging B, count value db reverse count £ ® the db to the segmentation, analysis, count set to better achieve the grating segmentation capabilities.
Comparative figure 3 and Figure 5 you can see, using FPGA design signal processing modules, design process and circuit structure more concise. Furthermore, in application note FPGA clock cycle should be less than the 1 grating signal pulse/4.
5 conclusions
① new design method of simple structure, high integration, than the traditional design of the device significantly reduced.
② integration design makes the system power consumption reduction, enhanced immunity to.
③ Verilog HDL design circuit used to change the circuit structure only need to modify the program, and system maintenance and upgrades of portability improve.
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