FPGA-based development of UART interface (1)

Design background

Serial port that is universal asynchronous receiver transmitter (UART, Universal Asynchronous Receiver Transmitter).

Serial communication with the transmission line low, low cost, high reliability, System Interconnection often using RS-232 interface, usually this interface consists of UART chip. But the UART interface chip General pin more containing many accessibility module and some accessibility, in the field tend to use these features, so if using UART chip that will inevitably lead to circuit complexity, PCB area increases, resulting in increased costs, reliability and stability of the system. Basic UART communication only need two signal cable (RXD and TXD), receive and send the form, which is full duplex TXD is the transmitter UART, RXD is UART's receive-side. Because of the increasingly powerful FPGA features, short development cycle, you can repeat programming advantages are more and more obvious, can be integrated in the FPGA chip UART function modules, which simplifies circuit, reduce PCB space and improve system reliability. In addition, FPGA design with high flexibility, you can easily upgrade and transplantation.

Design requirements

This interface as a content protection system part of the circuit board, is used primarily to communicate with the computer, and the other with UART interface board for communication.

Requirements for data transfer rate is not high, the transmission distance is not very long, but the transmission of data requires accurate and reliable. This interface can be used to monitor the internal State, set the circuit FPGA internal information output to the computer through the serial ports to achieve the purpose of the auxiliary debugging circuits. In addition, onboard FPGA hangs a serial Flash, available through the serial port on the Flash Debug data in the Flash output to your computer and data can be written through the serial port in Flash. In short, this interface is used as the computer and the Board of a reliable bi-directional data transmission channel.

Principle of the UART

UART asynchronous communication, communication of the sender and the receiver have independent clock, transmission rate by mutual agreement.

This design uses the most commonly used per second transmission speed 9600 baud.

UART communication protocol is very simple to low level as the start bit, stop bit as high level, intermediate can transfer 5 ~ 8 bit data and 1-bit parity bit, parity bits are and data bit length of the two sides agreed by the communication.

A data transfer completion can continue to transfer the next frame data, or you can continue to maintain a high level, two high level between frames, duration can be of arbitrary length. This solution does not add a parity bit is methodology to improve the efficiency of data transfer. Send-send data to a low level, and then send the 8 bits of data, immediately after the signal, high, thus completing a frame data transfer. The receiver receives a low level counting, and then receive 8 bit information bits after the detection of high level that has received a frame data, continue to wait for the next frame starting signal the arrival of low level, if received after 8 bit data does not detect a high level that it is not a valid data frames, dropped, continues to wait for the starting signal. Sequential relationships as shown in Figure 1, send and receive at the same time, do not disturb each other.

　　

　　

Figure 1 RS-232 interface work time series

Hardware circuit schematic diagram and description

An integrated RS-232 interface is a 25-pin D-type connector, 25-pin connector is really only 9 connector, resulting in a simplification of the 9-pin D-type RS-232 plug seat, commonly used is a 9-pin D-type plug.

Generally used only to send a signal line, one receives the signal line and a ground wire, and the rest of the ring indicator, the request is sent, the clear transfer, ready and waiting for the data carrier detect line can be suspended.

RS-232 standard logic 1 level as-15-0-3V, logic level is 3 ~ 15V.

CMOS circuit level range is usually from 0V to supply voltage, FPGA I/O input and output voltage is usually 0 ~ 3.3V, and FPGA supply voltage must be consistent, and level conversion chips. Selection of Maxim company MAX3232 level translation chip, circuit schematic diagram shown in Figure 2.

　　

　　

Figure 2 RS-232 interface circuit

Line with the most simple 3 wire connection mode, i.e. you only need two signal lines and ground to complete a send or receive data.

And FPGA only need to choose two normal i/o pins respectively and interface chip MAX3232 corresponding pin T2IN, R2OUT can be linked to through the serial port level translation work of the Board for the device, i.e. achieve level RS-232 level and TTL/CMOS level conversion. A MAX3232 chip can support two serial port-level transformation, we select one set of interfaces, the figure of four resistance can eliminate. In circuit joined 0 Ω jumper resistors, to this set of interfaces that you can easily skip lines, use a different set of interfaces.

Software design

Asynchronous receiver transmitter UART baud rate generator, the receiver and transmitter UART constitute three modules.

Is in every second transmission speed 9600 baud, and the system clock is 10MHz, this requires a rate change. In fact, since the circuit in interference factors such as sample data edge vulnerable to false, only the data of the Central sampling error probability can be reduced to a minimum, use 16 times the baud rate of the clock, i.e. 960016Hz =15600Hz。 So the baud rate generator output of clock frequency should be 15600Hz, UART and receive every data width are baud rate generator output clock cycle of 16 times, the use of Altera Corporation chip inside the PLL can be easily achieved. UART receiver and transmitter UART are made of Verilog language programming.

The data is typically used for parallel data, in order to facilitate and system interconnection, in other circuits UART receiver transmitter UART output data and input data are 8-bit parallel data.

UART receiver will receive the serial data and convert it into parallel data sent, UART dispatcher input of parallel data to UART serial data and follow the frame format output.

　　

　　

Figure 3 UART receiver symbol figure

Figure 3 symbols for UART receiver, rst is a global reset signal rxd as serial data input, the input clock, baudClk16x dataOut [7 ..0], for parallel data output to output data of irq indication signal.

The first sink waiting for the arrival of initiation, in each clock rising edge detection input data is a low level, to detect low level, you start to count, if continuous 8 clock input data are low level, the starting signal is considered valid, if there is a sample of the high level is considered the starting signal is invalid, the return to the initial state of the waiting for the starting signal again. Finds the starting signal valid after every 16 clock sampling time, so that you can guarantee that every data point out sampling, the sampling results into 8-bit shift register, 8 bit data sampling, the sampling interval to 16 clock stop bit. If you pick up a high level, then consider this frame data effectively, will shift registers in data parallel sent at the same time will output data indicates signal reset reset the high, and then sink, waiting for the arrival of the next frame; if the harvest is low level, you do not think it is a valid data, not the data in the shift register, output directly back to the initial state.

　　

　　

Figure 4 UART dispatcher symbol figure

Figure 4 the symbol for the transmitter UART, flag to enter data indicates the signal, the rst to be a global reset signal is input clock, clkin, din [7 ..0] for parallel data input, tdo for serial data output.

Sink in each clock's rising edge detection input data indicates the signal, if it detected it as a high level, then the parallel input data lock into the internal 8 bit shift register, next to send a low level and maintain 16 clock, then every 16 clock will shift register data is moved out in a bit, and finally send out high level that returns the initial state.

System debug

UART receiver and transmitter may act according to the actual need for separate use, but the convenience, the two docking, as shown in Figure 5.

UART receiver output and input is connected to the transmitter UART, the reset signal and shared with the clock signal, the clock signal outside by the Tablet, enter crystal oscillator provides FPGA by PLL frequency converting needs.

　　

　　

Figure 5 debugging system module diagram

Serial debugging needs with serial debugging tools, you can use VC programming, or you can directly use the Internet have debugging tools.

Direct selection of online serial debugging assistant has been tested, the data sent from the computer, after a UART interface to receive and then sent back to the computer. After several minutes of uninterrupted received and sent, will be sent back to the computer's data is compared with the original data, several tests have not been any errors, which fully describes the UART interface program with a high degree of reliability and stability, can meet the design requirements.

Closing remarks

Use FPGA to UART interface, you can reduce system PCB area, lower system power consumption, improve the design of the stability and reliability, and can take full advantage of the remainder of the FPGA resources.

Comprehensive report shows that a UART interface section only consumed 68 logical unit for FPGA, this resource is negligible, with so few resources they can to [1] [2]