Intelligent security monitoring and rapid reaction systems design and implementation (1)

Abstract: design of a rapid reaction embedded intelligent security monitoring system, moving target tracking, locating, fast capture facial images.

Using pattern recognition and image processing technology for facial feature extraction for analysis, and its characteristic quantities and face library feature to match the amount, whether or not to be illegal, and if you start alarm program.

With the improvement of living standards and the strengthening of security awareness, video monitoring system has been widely applied.

Current monitoring and control more to PC-based, you can only play a simple video recording function, also require special monitoring screen. For those few people access important places, through manual mode on the screen monitor is a chore, but PC also equipped with high-capacity hard drive to hold all of the video image, hard drive usage. To address this situation, this article has designed a unattended monitoring system. System in the range into the monitor does not save video image, when someone enters a monitoring areas will start the video recording of the program, while automatically fast capture face, using pattern recognition and image processing technology for facial feature extraction for analysis, and its characteristic quantities and face library features to match, determine whether the illegal workers, if the conduct of the police, and through remote monitoring center network reminder note. For seldom someone appears, use the monitoring system can reduce data capacity, reduce monitoring staff and do not worry about missing monitor object. This system is the original generation of products based on the hardware circuit design and software algorithms that have been improved. Proven system of reaction speed, speed, etc., are all recognition processing has been improved.

1 system overview

Camera control in the master system to work, in the absence of moving objects into the camera's data is not stored.

When someone enters into shooting the master system immediately control camera on illegal entry into the specified region of the human body for track and trace the process on face detection and quickly and accurately obtain the facial image, start the video recording feature at the same time; and then through a series of digital image processing methods on the facial image analysis and processing, to determine whether an attempted break-in, if you start the alarm system. Take advantage of more of these subsystems can form a monitoring network, various subsystems over a network connection with the monitoring center. Each subsystem has intelligent monitoring capabilities, so monitoring center only equipped with a duty officer to monitor more than 20 monitoring points, greatly reducing the use of the personnel.

2 system hardware

Because the system handle the data volumes larger and require real-time; it uses a combination of DSP and FPGA, coupled with the image data acquisition chip and memory chips that constitute the core image processing unit.

At the same time equipped with local alarm module, network transmission, etc, so as to constitute a complete surveillance system. System block diagram shown in Figure 1. Compared with the original system, this system made the following improvements: the original just as data buffered on-chip FPGA design for a master, control data input conditioning and output alarm, and the DSP, specifically used for image processing and transport. This can improve data processing speeds, thereby improving the responsiveness of the system.

2.1 system selection of major chip

(1) image acquisition chip adopts TVP5150.

TVP5150 with ultra-low power consumption, support NTSC/PAL/SECAM, format, high-performance video decoder. In normal working hours, it is only 115 mW of power consumption, by setting the internal registers, you can convert analog video signal YUV4: 2: 2 format ITU-R BT.656 digital signal, and direct to DM642 for processing.

(2) to provide a system of rapid reaction capabilities, image processing chip selection are particularly critical, complex factors, TI DSP selection of company-specific multimedia chip TMS320DM642 (hereinafter referred to as "DM642").

DM642 C64x kernel based, 720 MHz clock frequency, each instruction cycle can parallel 8 32 bit instructions that can reach 5 760 MIPS peak computation [6]. DM642 using level 2 cache structure (L1 and L2), which greatly improves the speed of the program. On-chip 64 bit the EMIF (External Memory Interface) interface to SDRAM and Flash memory, and so on for seamless connection, greatly facilitates the removal of large amounts of data. In addition, DM642 also owns three dedicated video port (VP0 ~ VP2) for receiving, processing, video and audio data, system extension is very convenient. In addition, DM642 the EMAC estuary and port extension from EMTF out ATA port, also when processing is complete of massive data provides storage channel [5]. DM642 need plus SDRAM (4-M64 bit) used to hold the procedure and cache digital video, and FLASH (4 M8 bit) for curing procedures for ROM boot.

(3) FPGA logic is responsible for implementing the system, output control, and internal cache timing control.

To achieve image real-time acquisition and processing, you need video acquisition and image processing work in parallel. Acquisition to the image data sent to the cache before the DSP interface design is crucial to the design of a direct impact on the responsiveness of the system. To increase the read speed of data cache, you can use FPGA internal resources to build high-speed dual-port RAM as the inner cache, the data frame processing alternate for data acquisition and processing at the same time, its internal structure shown in Figure 2, shown within the dotted line box. Acquisition of digital video signals through filtering, then fed into A logical unit, A responsible for generating clock and data logic control. Input video data in A control signal, into the buffer register b and c, and D in control unitControl, to a dual-port RAM. In order to achieve the real-time image acquisition and processing, makes FPGA for image data buffering and DSP read the image data will sync to RAM into equal 2 blocks, i.e. RAM1 and RAM2. In the system work, a piece for buffered image data, FPGA classification after signal buffer to write to the store; another piece of the DSP is used to read the image data, the DSP can be directly on the store of data operations. The cache structure of another feature is the FPGA and DSP on dual-port RAM addressing is switching back and forth. Because the DSP read RAM speed greater than the speed of the FPGA to write RAM, so the switching signal is issued only by the FPGA. When the FPGA classification buffered data is full RAM1, DSP FPGA to sending a break signal, at which point DSP read data in RAM1, FPGA RAM2 buffered data to be written. When data is full in RAM2, FPGA and DSP interrupt signal DSP read data in RAM2, RAM1 FPGA buffered data. So alternating image data read and write at the same time, which improves the speed of data processing.

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