VGA (Video Graphics Array) is in 1987 with the IBM PS/2 machines with the launch of a video transmission standard, with high resolution, fast display rate, color rich, etc., in the color display areas has been widely used.
Current VGA technology also is mainly based on VGA display card in your computer, notebook and other devices, but some require both showing color high resolution images without the need to use a computer device, but the technology of VGA is rare. This article on embedded VGA display method. Based on this design method of embedded VGA display system, you can not use VGA display card and computer, VGA image display and control. The system has a low cost, simple structure, flexible benefits, can be widely used in supermarkets, stations, airports and other public places advertising and prompt information display, also can be applied to the factory floor production operation information display, but also to multimedia applications in the life of ordinary. 1 display the realization principle and VGA timingGeneric VGA display card system consists of control circuits, display cache and video BIOS program is composed of three parts.
Control circuit shown in Figure 1. Control circuit main event, display the complete time series buffer data operations, main clock selection and D/A conversion, and other functions; display buffer provides display data cache space; video BIOS as control curing in display card ROM.1.1 VGA timing analysis
Through the VGA display card basic working principles of analysis shows that to achieve the VGA display is going to resolve the data source, data storage, sequential implementation issues, including key or how to implement a VGA timing.
VGA standard reference display timing as shown in Figure 2. Line sequential and frame timing synchronization pulses are needed to produce (Sync a), displayed along (Back porch b), the display timing (Display interval c) and display the front (Front porch d) four parts. Several common patterns of temporal parameter as shown in table 1.1.2 VGA timing implementation
First of all, according to the refresh rate to determine the main clock frequency, followed by the main clock frequency and the image resolution calculation the total number of cycles, the trip to table 1 for a, b, c, d the timing period of time in accordance with the main count pulse source frequency converted into the number of clock cycles.
In using the counter and CPLD RS trigger to the calculated each sequential segment of clock cycles, produce different width and cycle of pulse signal, and then use their logical combination of Figure 2 a, b, c, d the timing and d/a converter, blank signal BLANK and synchronous signal SYNC.1.3 read SRAM address generation method
Main clock as pixel count pulse signal while providing memory SRAM read signal and D/A conversion clock, it-driven counter output as read on the low address SRAM.
Line synchronization signal as row count pulse signal, it-driven counter outputs as read SRAM high address. As a result of two SRAM, so the top address as SRAM chip selected. Because the signal through the CPLD internal logic device when there is a certain time delay, CPLD generates address and read signal read data, read signal, address signal and data signals do not meet the time-series data of SRAM reading. You can use hardware circuit on reading some timing signal, the signal to be able to meet the reading of SRAM and as DAC input data timing requirements.1.4 data width and format
If true-color VGA display BMP images, you need the R, G, B three components, namely, the 8-bit to 24-bit value representing a pixel, in many cases also uses 32-bit represents a pixel value.
In order to save memory space, high color images may be used, that is, each pixel value represented by a 16-bit, R, G, B three components use the 5-bit, 6-digit, 5-bit than true color image to reduce by half the amount of data that meet the display effect.2 functional unit design
Realization of VGA display, in addition to achieve timing control, you must also have the support of other functional units in order to achieve the complete image is displayed.
(1) controller: VGA display a variety of modes, use the controller to switch among them, you also need to display the contents of the receipt, processing and display.
So the higher the performance of the controller, the data is updated and displays the results.(2) displays the data cache area: VGA display requires memory speed, large capacity.
Reading speed to reach 65MHz to BU, storage capacity at least 2MB. Can using high-speed SRAM or SDRAM as the display data cache.[1] [2]
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